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1.发明授权Digital system with an output buffer with a switching current settable to load-independent constant values 有权具有输出缓冲器的数字系统，其开关电流可设置为负载无关常数公开(公告)号：US06914457B2
公开(公告)日：2005-07-05
申请号：US10460035
申请日：2003-06-10
CPC分类号： H03K17/166 , H03K17/164
摘要： A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.
摘要翻译： 数字系统包括数字数据处理单元，连接到处理单元的至少一个输出缓冲器，以响应于从处理单元到达的数字信号产生输出信号，并且至少一个用户单元作为输出缓冲器负载进行连接。 为了确保输出缓冲器的开关电流可以被设置为不同的值，输出缓冲器包括用于将开关电流固定为基本上恒定且与负载无关的值的装置和用于选择性地设置 开关电流和处理单元包括用于存储预定参数的装置; 所述装置连接到选择设定装置，用于将切换电流的值设定为预定参数的函数。
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2.发明授权High speed, low power switched-capacitor digital-to-analog converter with a precharge arrangement 有权具有预充电布置的高速，低功率开关电容数模转换器公开(公告)号：US06621444B1
公开(公告)日：2003-09-16
申请号：US10174501
申请日：2002-06-17
IPC分类号： H03M112
摘要： A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages. The converter includes a circuit for monitoring the values of each bit of input digital codes, and a control circuit coupled to the first and second switching circuits to open or close selectively during a bit clock period the connections to the first, second, third, and fourth voltages according to the following criterion: when a bit value of the current input digital code Bj is equal to the corresponding bit value of the previous input digital code Bj−1, the first switching circuit is enabled and the second switching circuit is disabled during the whole bit clock period, and when the monitoring circuit detects a bit value of a current input digital code Bj to be different from the corresponding bit value of the previous input digital code Bj−1, the first switching circuit is disabled and the second switching circuit is enabled during a starting time portion of the bit clock period, while the first switching circuit is enabled and the second switching circuit is disabled during the remaining portion of the bit clock period.
摘要翻译： 开关电容器数模转换器包括用于提供第一和第二参考电压的第一电压发生器，用于提供第三和第四参考电压的第二电压发生器，所述第三和第四参考电压被选择以匹配第一和第二参考电压的预定设计值， 的二进制加权电容。 每个电容器具有连接到公共电路节点的第一电极，其连接到转换器输出端子和通过相关联的第一开关电路选择性地连接到第一和第二参考电压中的任一个的第二电极，或者通过相关联的 第二开关电路，到第三和第四参考电压中的任一个。 转换器包括用于监视每一位输入数字代码的值的电路，以及耦合到第一和第二开关电路的控制电路，用于在位时钟周期期间有选择地打开或关闭与第一，第二，第三和第 第四电压根据以下标准：当当前输入数字码Bj的位值等于先前输入数字码Bj-1的相应位值时，第一开关电路被使能，并且第二开关电路在 整个位时钟周期，并且当监视电路检测到当前输入数字码Bj的比特值与先前输入数字码Bj-1的对应比特值不同时，第一切换电路被禁用，第二切换 在位时钟周期的起始时间部分期间使能电路，而第一开关电路被使能并且第二开关电路在重新启动期间被禁止 占位时钟周期的一部分。
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3.发明授权
公开(公告)号：US5973537A
公开(公告)日：1999-10-26
申请号：US948986
申请日：1997-10-10
CPC分类号： H03F3/005 , H03F3/45946 , H03F2203/45421
摘要： In switch-capacitor systems for extremely low supply voltage, employing a fully differential switched op-amp, proper functioning of nMOS switches coupled to the inverting input node of an integrated stage capable of outputting a common mode control signal is made possible by retaining the ground potential on the input node to prevent body effects on the threshold of nMOS switches by means of an auxiliary switched capacitor.
摘要翻译： 在采用完全差分开关运算放大器的开关电容器系统中，通过使用完全差分开关运算放大器，可以通过保持接地来实现耦合到能够输出共模控制信号的集成级的反相输入节点的正常功能 输入节点上的电位，以通过辅助开关电容器来防止身体对nMOS开关阈值的影响。
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4.发明授权Integrated programmable gain amplifier circuit and system including the circuit 有权集成可编程增益放大器电路和系统包括电路公开(公告)号：US08044718B2
公开(公告)日：2011-10-25
申请号：US12637091
申请日：2009-12-14
申请人： Germano Nicollini , Angelo Nagari
发明人： Germano Nicollini , Angelo Nagari
IPC分类号： H03F1/36
CPC分类号： H03G1/0088 , H03F3/45475 , H03F2203/45526 , H03F2203/45594 , H03H11/126 , H03H11/1291
摘要： An integrated programmable gain amplifier circuit that receives at an input an analog signal, circuit including an operational amplifier and a gain setup network comprising resistive elements and selection elements, which may be controlled in order to setup the gain of the amplifier circuit. The gain setup network further includes capacitive elements, for defining, together with the resistive elements and the operational amplifier, an anti-aliasing filter of the active RC type.
摘要翻译： 一种集成可编程增益放大器电路，其在输入端接收模拟信号，包括运算放大器的电路和包括电阻元件和选择元件的增益设置网络，其可被控制以便建立放大器电路的增益。 增益设置网络还包括用于与电阻元件和运算放大器一起定义主动RC型的抗混叠滤波器的电容元件。
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公开(公告)号：US06556072B1
公开(公告)日：2003-04-29
申请号：US08791281
申请日：1997-01-30
申请人： Germano Nicollini , Angelo Nagari
发明人： Germano Nicollini , Angelo Nagari
IPC分类号： H03K500
CPC分类号： G11C27/024 , G11C27/026 , H03F3/005 , H03H19/004 , H03K5/249
摘要： A switched capacitor circuit comprising an operational amplifier, having first and second input terminals and an output terminal, the first input terminal being connected to a first reference potential. The operational amplifier is provided with a negative feedback network including a first capacitive element which is connected between the second input terminal and the output terminal of the operational amplifier, a second capacitive element which has a first terminal alternately connected to the second input terminal of the operational amplifier and to a reference potential, and a second terminal connected to a first circuit node which is alternately connected to a signal input terminal and said first output terminal of the operational amplifier. The circuit further includes a third capacitive element connected between the circuit node and a reference potential.
摘要翻译： 一种开关电容器电路，包括具有第一和第二输入端子的运算放大器和输出端子，所述第一输入端子连接到第一参考电位。 运算放大器设置有负反馈网络，其包括连接在运算放大器的第二输入端子和输出端子之间的第一电容元件，第二电容元件，其具有交替地连接到第二输入端子的第二输入端子 运算放大器和参考电位，以及连接到交替连接到运算放大器的信号输入端和所述第一输出端的第一电路节点的第二端。 电路还包括连接在电路节点和参考电位之间的第三电容元件。
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公开(公告)号：US06433724B1
公开(公告)日：2002-08-13
申请号：US09533015
申请日：2000-03-22
IPC分类号： H03M112
CPC分类号： H03M1/068 , H03M1/0845 , H03M1/468 , H03M1/804
摘要： A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm−Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.
摘要翻译： 根据二进制码加权的一组采样电容器以电压Vcm-Vin / 2通过第一电容单元充电，该电容单元的电容等于该组电容的和。 该转换通过比较器的SAR处理和与电容器相关的开关操作的逻辑单元进行。 开关的最终位置被加载到提供数字输出信号的寄存器中。 为了防止电源和参考电位源的任何干扰影响转换精度，提供两个另外的电容单元，其电容与第一电容单元相同。 这些可以防止比较器输入中的所有干扰在共模中，因此对输出没有任何影响。
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公开(公告)号：US5994960A
公开(公告)日：1999-11-30
申请号：US948562
申请日：1997-10-10
CPC分类号： H03F3/72 , H03F1/086 , H03F2200/513
摘要： In a switched operational amplifier including a differential input stage and at least a second output stage, the compensation capacitor commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with a switching circuit. The switching circuit is controlled by the same control phase that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.
摘要翻译： 在包括差分输入级和至少第二输出级的开关运算放大器中，将第二级的输出节点与放大器的输入差分级的相应输出节点耦合起来的补偿电容器与切换 电路。 开关电路由相同的控制相位控制，使得放大器能够在禁止放大器以减少开关电流的相位期间中断补偿电容器（CC）和差分输入级的输出节点之间的连接， 准时。 值得注意的是，运算放大器的差分输入级保持始终有效，只有第二个输出级接通和关断。
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公开(公告)号：US20140153732A1
公开(公告)日：2014-06-05
申请号：US14119512
申请日：2012-05-15
申请人： Christian Fraisse , Angelo Nagari
发明人： Christian Fraisse , Angelo Nagari
IPC分类号： G10K11/178
CPC分类号： G10K11/178 , H03F3/217 , H03K7/08
摘要： The electronic device and a corresponding signal processing method disclosed herein reduces electromagnetic noise. To that end, the electronic device includes a delay line, an oscillator, and a modulator. The delay line generates a spread spectrum clock signal from an input clock signal, where a timing jitter and a period of jitter of the spread spectrum clock signal are controlled at each period of the spread spectrum clock signal based on a digital code. The oscillator uses the spread spectrum clock signal to generate a processing signal. The modulator modulates the processing signal as a function of an audio signal.
摘要翻译： 本文公开的电子设备和相应的信号处理方法降低了电磁噪声。 为此，电子设备包括延迟线，振荡器和调制器。 延迟线从输入时钟信号产生扩频时钟信号，其中基于数字码在扩频时钟信号的每个周期处控制定时抖动和扩频时钟信号的抖动周期。 振荡器使用扩频时钟信号来产生处理信号。 调制器根据音频信号调制处理信号。
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公开(公告)号：US07283005B2
公开(公告)日：2007-10-16
申请号：US11055539
申请日：2005-02-09
IPC分类号： H03K3/03
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.
摘要翻译： 电路包括第一环形振荡器，其包括奇数个反相元件，延迟元件和输出端子; 延迟元件相对于输入脉冲的预定边缘以相对于输入脉冲的另一边缘基本上没有时间延迟的预定时间延迟在其输入端响应脉冲。 为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括具有连接到第一振荡器的输出端的输出端的第二环形振荡器和具有连接到第一振荡器的输出端的双稳态逻辑电路， 连接到第一和第二振荡器的公共输出端的输出端子。 第一振荡器的反相元件和第二振荡器的反相元件中的至少一个的至少一个构成双稳态逻辑电路的一部分。
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10.发明授权High resolution, high speed, low power switched capacitor digital to analog converter 有权高分辨率，高速度，低功耗开关电容数字到模拟转换器公开(公告)号：US06600437B1
公开(公告)日：2003-07-29
申请号：US10115272
申请日：2002-04-01
IPC分类号： H03M166
摘要： A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2p−1)·Cs−CATT=2p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.
摘要翻译： 开关电容器数模转换器包括具有相应的第二和第二二进制加权电容器阵列的第一和第二转换器段。 第一段的每个电容器具有连接到第一公共节点的第一电极和通过各个开关连接到第一和第二参考电压端子之一的第二电极。 第二段的每个电容器具有连接到第二公共节点的第一电极和通过各个开关连接到第一和第二参考电压端子之一的第二电极。 该转换器包括连接在第一和第二公共节点之间的耦合电容器和连接在第一公共节点和参考电压端子之间的电容装置。 耦合电容器和电容装置分别具有电容Cs和CATT，其基本上满足以下关系：（2p-1）.C-CATT = 2p.C，其中p是在第一转换器段中编码的位数，C是 单位电容。
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