-
1.发明授权High speed, low power switched-capacitor digital-to-analog converter with a precharge arrangement 有权具有预充电布置的高速，低功率开关电容数模转换器公开(公告)号：US06621444B1
公开(公告)日：2003-09-16
申请号：US10174501
申请日：2002-06-17
IPC分类号： H03M112
摘要： A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages. The converter includes a circuit for monitoring the values of each bit of input digital codes, and a control circuit coupled to the first and second switching circuits to open or close selectively during a bit clock period the connections to the first, second, third, and fourth voltages according to the following criterion: when a bit value of the current input digital code Bj is equal to the corresponding bit value of the previous input digital code Bj−1, the first switching circuit is enabled and the second switching circuit is disabled during the whole bit clock period, and when the monitoring circuit detects a bit value of a current input digital code Bj to be different from the corresponding bit value of the previous input digital code Bj−1, the first switching circuit is disabled and the second switching circuit is enabled during a starting time portion of the bit clock period, while the first switching circuit is enabled and the second switching circuit is disabled during the remaining portion of the bit clock period.
摘要翻译： 开关电容器数模转换器包括用于提供第一和第二参考电压的第一电压发生器，用于提供第三和第四参考电压的第二电压发生器，所述第三和第四参考电压被选择以匹配第一和第二参考电压的预定设计值， 的二进制加权电容。 每个电容器具有连接到公共电路节点的第一电极，其连接到转换器输出端子和通过相关联的第一开关电路选择性地连接到第一和第二参考电压中的任一个的第二电极，或者通过相关联的 第二开关电路，到第三和第四参考电压中的任一个。 转换器包括用于监视每一位输入数字代码的值的电路，以及耦合到第一和第二开关电路的控制电路，用于在位时钟周期期间有选择地打开或关闭与第一，第二，第三和第 第四电压根据以下标准：当当前输入数字码Bj的位值等于先前输入数字码Bj-1的相应位值时，第一开关电路被使能，并且第二开关电路在 整个位时钟周期，并且当监视电路检测到当前输入数字码Bj的比特值与先前输入数字码Bj-1的对应比特值不同时，第一切换电路被禁用，第二切换 在位时钟周期的起始时间部分期间使能电路，而第一开关电路被使能并且第二开关电路在重新启动期间被禁止 占位时钟周期的一部分。
-
2.发明授权High-speed, high-resolution and low-consumption analog/digital converter with single-ended input 有权具有单端输入的高速，高分辨率和低功耗模拟/数字转换器公开(公告)号：US06897801B2
公开(公告)日：2005-05-24
申请号：US10483790
申请日：2002-06-13
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/804
摘要： An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.
摘要翻译： 一种A / D转换器，具有电容器，其具有以二进制代码加权的采样电容器的第一阵列阵列，连接在第一公共电路节点和待充电的输入端子之间，所述第一公共电路节点和输入端子相对于要转换的信号的接地为输入电压， 然后根据SAR技术选择性地与两个差分参考端子连接，并且同时等效于第一和所有连接到第二节点的第二阵列的电容器选择性地连接到地和下差分电压端子。 两个节点连接到比较器的相应输入端。 逻辑单元根据预定的定时程序和作为比较器的输出的函数来控制两个阵列的电容器的连接。
-
公开(公告)号：US07212143B1
公开(公告)日：2007-05-01
申请号：US11336657
申请日：2006-01-20
IPC分类号： H03M1/12
CPC分类号： H03M1/1225
摘要： A circuit for selectively converting at least one analog signal into corresponding digital codes. The circuit includes a management block having a plurality of inputs, each adapted for receiving a respective request signal carrying a request to convert the at least one analog signal. The management block is adapted to assign a priority level to the request signals based upon the input where the request signals are received, and is further operative to select one of the request signals based upon the assigned priority level and output a conversion start-up signal corresponding to the selected request signal. The circuit has a conversion block for receiving east one analog signal input and is connected to the management block to receive the conversion start-up signal as input, and start up conversion of the at least one analog signal.
摘要翻译： 用于选择性地将至少一个模拟信号转换成相应数字码的电路。 电路包括具有多个输入的管理块，每个输入适于接收携带转换所述至少一个模拟信号的请求的相应请求信号。 管理块适于基于接收到请求信号的输入来为请求信号分配优先级，并且还可操作以基于所分配的优先级来选择一个请求信号，并输出转换启动信号 对应于所选择的请求信号。 电路具有用于接收东一模拟信号输入的转换块，并连接到管理块以接收转换启动信号作为输入，并启动至少一个模拟信号的转换。
-
公开(公告)号：US20050231293A1
公开(公告)日：2005-10-20
申请号：US11055539
申请日：2005-02-09
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.
摘要翻译： 电路包括第一环形振荡器，其包括奇数个反相元件，延迟元件和输出端子; 延迟元件相对于输入脉冲的预定边缘以相对于输入脉冲的另一边缘基本上没有时间延迟的预定时间延迟在其输入端响应脉冲。 为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括具有连接到第一振荡器的输出端的输出端的第二环形振荡器和具有连接到第一振荡器的输出端的双稳态逻辑电路， 连接到第一和第二振荡器的公共输出端的输出端子。 第一振荡器的反相元件和第二振荡器的反相元件中的至少一个的至少一个构成双稳态逻辑电路的一部分。
-
5.发明授权High resolution, high speed, low power switched capacitor analog to digital converter 有权高分辨率，高速度，低功耗开关电容模拟数字转换器公开(公告)号：US06686865B2
公开(公告)日：2004-02-03
申请号：US10455894
申请日：2003-06-06
IPC分类号： H03M112
摘要： An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2p−1)·Cs−CATT=2p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.
摘要翻译： 模数转换器包括具有相应的二进制加权电容器的第一和第二阵列的第一和第二转换器段。 第一段的每个电容器具有连接到第一公共节点的第一电极和通过各个开关连接到第一参考电压端子和输入端子之一的第二电极。 第二段的每个电容器具有连接到第二公共节点的第一电极和通过相应开关连接到第一参考电压端子和输入端子之一的第二电极。 该转换器包括连接在第一和第二公共节点之间的耦合电容器和连接在第一公共节点和参考电压端子之间的电容装置。 耦合电容器和电容装置分别具有电容Cs和CATT，其基本上满足以下关系：（2
-1）.C-CATT = 2·C，其中p是在 第一转换器段，C为单位电容。
-
公开(公告)号：US07283005B2
公开(公告)日：2007-10-16
申请号：US11055539
申请日：2005-02-09
IPC分类号： H03K3/03
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.
摘要翻译： 电路包括第一环形振荡器，其包括奇数个反相元件，延迟元件和输出端子; 延迟元件相对于输入脉冲的预定边缘以相对于输入脉冲的另一边缘基本上没有时间延迟的预定时间延迟在其输入端响应脉冲。 为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括具有连接到第一振荡器的输出端的输出端的第二环形振荡器和具有连接到第一振荡器的输出端的双稳态逻辑电路， 连接到第一和第二振荡器的公共输出端的输出端子。 第一振荡器的反相元件和第二振荡器的反相元件中的至少一个的至少一个构成双稳态逻辑电路的一部分。
-
7.发明授权High resolution, high speed, low power switched capacitor digital to analog converter 有权高分辨率，高速度，低功耗开关电容数字到模拟转换器公开(公告)号：US06600437B1
公开(公告)日：2003-07-29
申请号：US10115272
申请日：2002-04-01
IPC分类号： H03M166
摘要： A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2p−1)·Cs−CATT=2p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.
摘要翻译： 开关电容器数模转换器包括具有相应的第二和第二二进制加权电容器阵列的第一和第二转换器段。 第一段的每个电容器具有连接到第一公共节点的第一电极和通过各个开关连接到第一和第二参考电压端子之一的第二电极。 第二段的每个电容器具有连接到第二公共节点的第一电极和通过各个开关连接到第一和第二参考电压端子之一的第二电极。 该转换器包括连接在第一和第二公共节点之间的耦合电容器和连接在第一公共节点和参考电压端子之间的电容装置。 耦合电容器和电容装置分别具有电容Cs和CATT，其基本上满足以下关系：（2p-1）.C-CATT = 2p.C，其中p是在第一转换器段中编码的位数，C是 单位电容。
-
公开(公告)号：US06433724B1
公开(公告)日：2002-08-13
申请号：US09533015
申请日：2000-03-22
IPC分类号： H03M112
CPC分类号： H03M1/068 , H03M1/0845 , H03M1/468 , H03M1/804
摘要： A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm−Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.
摘要翻译： 根据二进制码加权的一组采样电容器以电压Vcm-Vin / 2通过第一电容单元充电，该电容单元的电容等于该组电容的和。 该转换通过比较器的SAR处理和与电容器相关的开关操作的逻辑单元进行。 开关的最终位置被加载到提供数字输出信号的寄存器中。 为了防止电源和参考电位源的任何干扰影响转换精度，提供两个另外的电容单元，其电容与第一电容单元相同。 这些可以防止比较器输入中的所有干扰在共模中，因此对输出没有任何影响。
-
9.发明授权Digital system with an output buffer with a switching current settable to load-independent constant values 有权具有输出缓冲器的数字系统，其开关电流可设置为负载无关常数公开(公告)号：US06914457B2
公开(公告)日：2005-07-05
申请号：US10460035
申请日：2003-06-10
CPC分类号： H03K17/166 , H03K17/164
摘要： A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.
摘要翻译： 数字系统包括数字数据处理单元，连接到处理单元的至少一个输出缓冲器，以响应于从处理单元到达的数字信号产生输出信号，并且至少一个用户单元作为输出缓冲器负载进行连接。 为了确保输出缓冲器的开关电流可以被设置为不同的值，输出缓冲器包括用于将开关电流固定为基本上恒定且与负载无关的值的装置和用于选择性地设置 开关电流和处理单元包括用于存储预定参数的装置; 所述装置连接到选择设定装置，用于将切换电流的值设定为预定参数的函数。
-
10.发明授权Current steering digital-analog converter particularly insensitive to packaging stresses 有权电流转向数模转换器特别对包装应力不敏感公开(公告)号：US07675449B2
公开(公告)日：2010-03-09
申请号：US12172692
申请日：2008-07-14
IPC分类号： H03M1/66
CPC分类号： H03M1/0648 , H03M1/687 , H03M1/747
摘要： A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two.
摘要翻译： 一种用于将数字代码转换为模拟信号的电流转向数模转换器，所述转换器包括半导体材料的衬底，集成在衬底中的电流发生器的阵列，公共求和节点和基于数字代码可控的开关 用于将当前发生器连接到和从公共求和节点断开连接。 电流发生器适于根据与发电机阵列的电流发生器提供给求和节点的单位电流值相比的功率，为公共求和节点提供具有多个值的电流。 电流发生器被分成基本数量的模块化电流产生元件，彼此平行至少等于2。
-
-
-
-
-
-
-
-
-
搜索结果
62 条记录 (耗时 0.018 秒)
