利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

111 条记录 (耗时 0.031 秒)

    POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS
    1.
    发明申请
    POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS 有权
    无连接和低ULK损伤集成方案用于大型互连

    公开(公告)号：US20080305625A1

    公开(公告)日：2008-12-11

    申请号：US11759451

    申请日：2007-06-07

    申请人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    发明人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76811 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

    摘要翻译： 公开了一种形成双镶嵌结构的方法。 在超低k膜上沉积下介电硬掩模层和上绝缘硬掩模层。 在上部硬掩模层中形成第一通孔。 接下来，使用三层抗蚀剂方案形成第一沟槽。 最后，同时形成完整通孔和全沟槽。 可以在超低k层中使用可选的蚀刻停止层来控制沟槽深度。

    Poison-free and low ULK damage integration scheme for damascene interconnects
    2.
    发明授权
    Poison-free and low ULK damage integration scheme for damascene interconnects 有权
    无毒低密度ULK损伤集成方案，用于大马士革互连

    公开(公告)号：US08008200B2

    公开(公告)日：2011-08-30

    申请号：US13023315

    申请日：2011-02-08

    申请人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    发明人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76811 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

    摘要翻译： 公开了一种形成双镶嵌结构的方法。 在超低k膜上沉积下介电硬掩模层和上绝缘硬掩模层。 在上部硬掩模层中形成第一通孔。 接下来，使用三层抗蚀剂方案形成第一沟槽。 最后，同时形成完整通孔和全沟槽。 可以在超低k层中使用可选的蚀刻停止层来控制沟槽深度。

    POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS
    3.
    发明申请
    POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS 有权
    无连接和低ULK损伤集成方案用于大型互连

    公开(公告)号：US20110143533A1

    公开(公告)日：2011-06-16

    申请号：US13023315

    申请日：2011-02-08

    申请人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    发明人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76811 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

    摘要翻译： 公开了一种形成双镶嵌结构的方法。 在超低k膜上沉积下介电硬掩模层和上绝缘硬掩模层。 在上部硬掩模层中形成第一通孔。 接下来，使用三层抗蚀剂方案形成第一沟槽。 最后，同时形成完整通孔和全沟槽。 可以在超低k层中使用可选的蚀刻停止层来控制沟槽深度。

    Poison-free and low ULK damage integration scheme for damascene interconnects
    4.
    发明授权
    Poison-free and low ULK damage integration scheme for damascene interconnects 有权
    无毒低密度ULK损伤集成方案，用于大马士革互连

    公开(公告)号：US07884019B2

    公开(公告)日：2011-02-08

    申请号：US11759451

    申请日：2007-06-07

    申请人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    发明人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76811 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

    摘要翻译： 公开了一种形成双镶嵌结构的方法。 在超低k膜上沉积下介电硬掩模层和上绝缘硬掩模层。 在上部硬掩模层中形成第一通孔。 接下来，使用三层抗蚀剂方案形成第一沟槽。 最后，同时形成完整通孔和全沟槽。 可以在超低k层中使用可选的蚀刻停止层来控制沟槽深度。

    METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FABRICATION
    5.
    发明申请
    METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FABRICATION 审中-公开
    用于防止集成电路制造过程中的耐药性的方法

    公开(公告)号：US20080057701A1

    公开(公告)日：2008-03-06

    申请号：US11469598

    申请日：2006-09-01

    申请人： Edward Raymond Engbrecht ,  William W. Dostalik ,  Ping Jiang ,  Edmund Burke ,  Laura M. Matz

    发明人： Edward Raymond Engbrecht ,  William W. Dostalik ,  Ping Jiang ,  Edmund Burke ,  Laura M. Matz

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/31144

    摘要： A method of manufacturing an integrated circuit comprising fabricating a dual damascene interconnect. Fabricating the interconnect including forming a via opening in a surface of an inter-layer dielectric (ILD) located over a semiconductor substrate. Fabricating the interconnect also includes depositing a sacrificial fill material over the surface and in the via opening. Fabricating the interconnect further includes removing the sacrificial fill material from the surface, depositing a poison-blocking-layer over the surface and forming a trench pattern in a photoresist layer formed over the poison-blocking-layer. The poison-blocking-layer is configured to prevent poisons from entering the photoresist layer.

    摘要翻译： 一种制造集成电路的方法，包括制造双镶嵌互连。 制造互连，包括在位于半导体衬底上的层间电介质（ILD）的表面中形成通孔。 制造互连件还包括在表面上和通孔开口中沉积牺牲填充材料。 制造互连还包括从表面去除牺牲填充材料，在表面上沉积毒物阻挡层并在形成在毒物阻挡层上的光致抗蚀剂层中形成沟槽图案。 毒物阻断层被配置为防止毒物进入光致抗蚀剂层。

    Process for preparing rubber compositions and articles made therefrom
    6.
    发明授权
    Process for preparing rubber compositions and articles made therefrom 有权

    公开(公告)号：US10023723B2

    公开(公告)日：2018-07-17

    申请号：US11810300

    申请日：2007-06-05

    申请人： Ping Jiang ,  Robert James Perry

    发明人： Ping Jiang ,  Robert James Perry

    IPC分类号： C08K5/31 ,  C08K5/54 ,  C08K5/548

    摘要： A process for preparing a rubber composition comprises: (a) forming a mixture of: (i) at least one thiocarboxyl-functional hydrolyzable silane, (ii) at least one rubber containing carbon-carbon double bonds, (iii) at least one silane-reactive filler, (iv) at least one activating agent, and (v) water; (b) mixing the composition formed in step (a) under reactive-mechanical-working conditions and in the absence of vulcanizing agent(s); (c) adding at least one vulcanizing agent (vi) to the composition of step (b); (d) mixing the composition of step (c) under non-reactive-mechanical-working conditions; and, (e) optionally, curing the rubber composition of step (d).