Abstract:
A through silicon via (TSV) stacked structure made of stacked substrates. Each substrate includes multiple tapered through silicon vias, wherein the wider end of each tapered through silicon via is provided with a recessed portion and the narrower end of each tapered through silicon via protrudes from the substrate. The substrates are stacked one after another with the narrower end of each tapered through silicon via being fitting and jointing into a corresponding recessed portion of the tapered through silicon via.
Abstract:
A semiconductor package structure includes a package substrate having a first surface, a second surface opposite to the first surface, and a sidewall surface between the first surface and the second surface. A semiconductor device is mounted on the first surface. A mold cap encapsulates the semiconductor device. The mold cap includes a vertical extension portion covering the sidewall surface and a horizontal extension portion covering a periphery of a solder ball implanting region on the second surface.
Abstract:
A package substrate is disclosed. The package substrate includes a base layer and a dam structure or a dent structure on at least one side of the base layer. The base layer may be a CCL core, a molding compound, or an epoxy base.
Abstract:
A through silicon via (TSV) stacked structure made of stacked substrates. Each substrate includes multiple tapered through silicon vias, wherein the wider end of each tapered through silicon via is provided with a recessed portion and the narrower end of each tapered through silicon via protrudes from the substrate. The substrates are stacked one after another with the narrower end of each tapered through silicon via being fitting and jointing into a corresponding recessed portion of the tapered through silicon via.