公开(公告)号：US09620368B2

公开(公告)日：2017-04-11

申请号：US15175008

申请日：2016-06-06

申请人： Powerchip Technology Corporation

发明人： Chien-Lung Chu ,  Chun-Hung Chen ,  Ta-Chien Chiu

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40 ,  H01L21/3105 ,  H01L27/088 ,  H01L27/11521 ,  H01L27/11531

CPC分类号： H01L21/28035 ,  H01L21/2815 ,  H01L21/31055 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4925 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.

公开(公告)号：US09780195B2

公开(公告)日：2017-10-03

申请号：US14639087

申请日：2015-03-04

申请人： Powerchip Technology Corporation

发明人： Chien-Lung Chu ,  Chun-Hung Chen ,  Ta-Chien Chiu

IPC分类号： H01L27/11 ,  H01L29/66 ,  H01L27/11565 ,  H01L29/78 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7827

摘要： A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory cells. The first dielectric layer is disposed on the substrate. The memory cells are stacked on the first dielectric layer. Each of the memory cells includes two first conductive layers and a charge storage structure. The charge storage structure is disposed between the two first conductive layers. The charge storage structures in the vertically adjacent memory cells are separated from each other. The channel layer is disposed on a sidewall of the stacked structure and connected to the substrate. The second dielectric layer is disposed between the channel layer and the first conductive layers.

公开(公告)号：US09397183B2

公开(公告)日：2016-07-19

申请号：US14602283

申请日：2015-01-22

申请人： Powerchip Technology Corporation

发明人： Chien-Lung Chu ,  Chun-Hung Chen ,  Ta-Chien Chiu

IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/28 ,  H01L27/088 ,  H01L27/115

CPC分类号： H01L21/28035 ,  H01L21/2815 ,  H01L21/31055 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4925 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first dielectric layer thereon, and a shallow trench isolation (STI) in the substrate and surrounding the first gate layer and the first dielectric layer; removing the first dielectric layer; forming a first spacer on the sidewall of the STI above the first gate layer; and using the first spacer as mask to remove part of the first gate layer and part of the substrate for forming a first opening while defining a first gate structure and a second gate structure.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供在其上具有第一栅极层和第一介电层的衬底和衬底中的浅沟槽隔离（STI），并围绕第一栅极层和第一介电层; 去除第一电介质层; 在第一栅极层上方的STI的侧壁上形成第一间隔物; 以及使用所述第一间隔物作为掩模以除去所述第一栅极层的一部分和用于形成第一开口的所述衬底的一部分，同时限定第一栅极结构和第二栅极结构。

公开(公告)号：US20160284551A1

公开(公告)日：2016-09-29

申请号：US15175008

申请日：2016-06-06

申请人： Powerchip Technology Corporation

发明人： Chien-Lung Chu ,  Chun-Hung Chen ,  Ta-Chien Chiu

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/66 ,  H01L27/115 ,  H01L29/40 ,  H01L29/49 ,  H01L21/762

CPC分类号： H01L21/28035 ,  H01L21/2815 ,  H01L21/31055 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4925 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.

摘要翻译： 公开了半导体器件的制造方法。 提供了其上具有第一栅极层和第一介电层的基板。 在衬底中形成浅沟槽隔离（STI）并围绕第一栅极层和第一介电层。 去除第一介电层。 在第一栅极层上方的STI的侧壁上形成第一间隔物。 使用第一间隔件作为掩模，去除部分第一栅极层和基板的一部分以形成第一开口，同时限定第一栅极结构和第二栅极结构。

公开(公告)号：US20160211209A1

公开(公告)日：2016-07-21

申请号：US14672238

申请日：2015-03-30

申请人： Powerchip Technology Corporation

发明人： Hsin-Min Wu ,  Chien-Lung Chu ,  Chun-Hung Chen ,  Ta-Chien Chiu

IPC分类号： H01L23/528 ,  H01L21/02 ,  H01L29/06

CPC分类号： H01L29/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate, a plurality of composite layers, and at least one composite pillar. The substrate includes a first region and a second region. The composite layers are disposed on the substrate. Each of the composite layers includes at least one exposed surface and at least one sidewall. At least one staircase structure is formed by the exposed surface and the sidewall. The composite pillar is disposed on the exposed surface of the substrate.

摘要翻译： 提供半导体结构和制造半导体结构的方法。 半导体结构包括基板，多个复合层和至少一个复合柱。 衬底包括第一区域和第二区域。 复合层设置在基板上。 每个复合层包括至少一个暴露表面和至少一个侧壁。 至少一个阶梯结构由暴露的表面和侧壁形成。 复合柱设置在基板的暴露表面上。

公开(公告)号：US20160190150A1

公开(公告)日：2016-06-30

申请号：US14639087

申请日：2015-03-04

申请人： Powerchip Technology Corporation

发明人： Chien-Lung Chu ,  Chun-Hung Chen ,  Ta-Chien Chiu

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7827

摘要： A non-volatile memory includes a substrate, a stacked structure, a channel layer, and a second dielectric layer. The stacked structure includes a first dielectric layer and a plurality of memory cells. The first dielectric layer is disposed on the substrate. The memory cells are stacked on the first dielectric layer. Each of the memory cells includes two first conductive layers and a charge storage structure. The charge storage structure is disposed between the two first conductive layers. The charge storage structures in the vertically adjacent memory cells are separated from each other. The channel layer is disposed on a sidewall of the stacked structure and connected to the substrate. The second dielectric layer is disposed between the channel layer and the first conductive layers.

摘要翻译： 非易失性存储器包括衬底，层叠结构，沟道层和第二介电层。 堆叠结构包括第一电介质层和多个存储单元。 第一介电层设置在基板上。 存储单元层叠在第一电介质层上。 每个存储单元包括两个第一导电层和电荷存储结构。 电荷存储结构设置在两个第一导电层之间。 垂直相邻的存储单元中的电荷存储结构彼此分离。 沟道层设置在层叠结构的侧壁上并连接到衬底。 第二电介质层设置在沟道层和第一导电层之间。

公开(公告)号：US20160104785A1

公开(公告)日：2016-04-14

申请号：US14602283

申请日：2015-01-22

申请人： Powerchip Technology Corporation

发明人： Chien-Lung Chu ,  Chun-Hung Chen ,  Ta-Chien Chiu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L21/762 ,  H01L27/115 ,  H01L21/3105 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/40

CPC分类号： H01L21/28035 ,  H01L21/2815 ,  H01L21/31055 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4925 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first dielectric layer thereon, and a shallow trench isolation (STI) in the substrate and surrounding the first gate layer and the first dielectric layer; removing the first dielectric layer; forming a first spacer on the sidewall of the STI above the first gate layer; and using the first spacer as mask to remove part of the first gate layer and part of the substrate for forming a first opening while defining a first gate structure and a second gate structure.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供在其上具有第一栅极层和第一介电层的衬底和衬底中的浅沟槽隔离（STI），并围绕第一栅极层和第一介电层; 去除第一电介质层; 在第一栅极层上方的STI的侧壁上形成第一间隔物; 以及使用所述第一间隔物作为掩模以除去所述第一栅极层的一部分和用于形成第一开口的所述衬底的一部分，同时限定第一栅极结构和第二栅极结构。