METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT
    1.
    发明申请
    METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT 有权
    通过自动基于方法的控制和管理,峰值功率执行的方法和系统

    公开(公告)号:US20090089602A1

    公开(公告)日:2009-04-02

    申请号:US11862559

    申请日:2007-09-27

    IPC分类号: G06F1/28

    摘要: A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.

    摘要翻译: 一种连接组件的系统的电源管理方法包括:在所连接的组件之间初始化令牌分配映射,其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算,监视利用率传感器输入和命令 状态向量输入,基于所述利用传感器输入和所述命令状态向量输入,以第一周期性时间间隔确定所述系统的当前性能水平,当前功耗级别和所分配的功率预算,以及在所述第二周期时间 间隔,基于当前性能水平的令牌重新分配图,当前功耗水平和系统的分配的功率预算,根据至少一个连接的组件的重新分配的功率预算,同时执行功率 基于系统中分配的令牌总数的消耗限制。

    Method and system of peak power enforcement via autonomous token-based control and management
    2.
    发明授权
    Method and system of peak power enforcement via autonomous token-based control and management 有权
    通过自主的基于令牌的控制和管理来实现峰值功率的方法和系统

    公开(公告)号:US07930578B2

    公开(公告)日:2011-04-19

    申请号:US11862559

    申请日:2007-09-27

    摘要: A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.

    摘要翻译: 一种连接组件的系统的电源管理方法包括:在所连接的组件之间初始化令牌分配映射,其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算,监视利用率传感器输入和命令 状态向量输入,基于所述利用传感器输入和所述命令状态向量输入,以第一周期性时间间隔确定所述系统的当前性能水平,当前功耗级别和所分配的功率预算,以及在所述第二周期时间 间隔,基于当前性能水平的令牌重新分配图,当前功耗水平和系统的分配的功率预算,根据至少一个连接的组件的重新分配的功率预算,同时执行功率 基于系统中分配的令牌总数的消耗限制。

    Interlocked synchronous pipeline clock gating
    6.
    发明申请
    Interlocked synchronous pipeline clock gating 有权
    联锁同步管道时钟门控

    公开(公告)号:US20060161795A1

    公开(公告)日:2006-07-20

    申请号:US11375989

    申请日:2006-03-14

    IPC分类号: G06F1/26

    摘要: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

    摘要翻译: 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发,并且由失速信号单独且有选择地停止。 对于每个阶段,产生相对于下游级的失速信号延迟的失速信号,并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择,使得仅有有效数据的阶段停滞。

    Synchronous pipeline with normally transparent pipeline stages
    7.
    发明申请
    Synchronous pipeline with normally transparent pipeline stages 有权
    具有正常透明管线级的同步管道

    公开(公告)号:US20050251699A1

    公开(公告)日:2005-11-10

    申请号:US10838621

    申请日:2004-05-04

    申请人: Hans Jacobson

    发明人: Hans Jacobson

    CPC分类号: G06F9/3869 G06F1/10 G06F5/08

    摘要: A synchronous pipeline segment and an integrated circuit (IC) including the segment. The segment includes an input stage, an output stage and at least one intermediate stage. A place holder latch associated with each stage indicates whether valid stage data is in the stage. A local clock buffer provides a local clock gating a corresponding stage. The input and output stages are normally opaque and intermediate stages are normally transparent. Data items pass locally asynchronously between the input and output stages and are separated by opaque gated intermediate stages.

    摘要翻译: 同步管道段和包括该段的集成电路(IC)。 该段包括输入级,输出级和至少一个中间级。 与每个阶段相关联的占位符锁存器表示有效级数据是否处于阶段。 本地时钟缓冲器提供本地时钟门控相应的级。 输入和输出级通常是不透明的,中间级通常是透明的。 数据项在输入和输出级之间异步传递,并由不透明门控中间级分隔。

    System and method for topology selection to minimize leakage power during synthesis
    9.
    发明申请
    System and method for topology selection to minimize leakage power during synthesis 失效
    用于拓扑选择的系统和方法,以最大限度地减少合成期间的泄漏功率

    公开(公告)号:US20050125761A1

    公开(公告)日:2005-06-09

    申请号:US10731840

    申请日:2003-12-09

    IPC分类号: G06F17/50

    CPC分类号: G06F17/505

    摘要: A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology and the leakage sensitivities for each of the topologies is calculated. The system is then configured to synthesize a new circuit model by selecting one or more of the topologies based on its leakage sensitivities, wherein the new circuit model has reduced current leakage.

    摘要翻译: 一种用于在合成期间最小化泄漏功率的拓扑选择的系统,其中所述系统被配置为接收具有一个或多个电路门的电路模型。 该系统还被配置为接收具有一个或多个逻辑门的库,其中每个逻辑门具有拓扑,并且计算每个拓扑的泄漏灵敏度。 然后,该系统被配置为通过基于其泄漏灵敏度选择一个或多个拓扑来合成新的电路模型,其中新的电路模型具有减少的电流泄漏。