摘要:
A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要:
A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要:
A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchical architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要:
A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要:
A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要:
A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要:
A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要:
A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要:
An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要:
An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.