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1.发明申请METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT 有权通过自动基于方法的控制和管理，峰值功率执行的方法和系统公开(公告)号：US20090089602A1
公开(公告)日：2009-04-02
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/28
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。
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2.发明授权Method and system of peak power enforcement via autonomous token-based control and management 有权通过自主的基于令牌的控制和管理来实现峰值功率的方法和系统公开(公告)号：US07930578B2
公开(公告)日：2011-04-19
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。
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3.发明授权Method and system for controlling power in a chip through a power-performance monitor and control unit 有权通过功率监控和控制单元控制芯片功率的方法和系统公开(公告)号：US07421601B2
公开(公告)日：2008-09-02
申请号：US11357612
申请日：2006-02-17
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchical architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每个层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，而较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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4.发明授权Method and system for controlling power in a chip through a power performance monitor and control unit 有权通过功率性能监测和控制单元控制芯片功率的方法和系统公开(公告)号：US08639955B2
公开(公告)日：2014-01-28
申请号：US13292712
申请日：2011-11-09
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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5.发明授权Method and system for controlling power in a chip through a power-performance monitor and control unit 失效通过功率监控和控制单元控制芯片功率的方法和系统公开(公告)号：US08112642B2
公开(公告)日：2012-02-07
申请号：US12132044
申请日：2008-06-03
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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6.发明申请METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT 有权通过功率性能监视器和控制单元控制芯片中的功率的方法和系统公开(公告)号：US20120054528A1
公开(公告)日：2012-03-01
申请号：US13292712
申请日：2011-11-09
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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7.发明申请METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT 失效通过功率性能监视器和控制单元控制芯片中的功率的方法和系统公开(公告)号：US20090049318A1
公开(公告)日：2009-02-19
申请号：US12132044
申请日：2008-06-03
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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8.发明授权公开(公告)号：US06946869B2
公开(公告)日：2005-09-20
申请号：US10685863
申请日：2003-10-15
申请人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
发明人： Hans M. Jacobson , Pradip Bose , Alper Buyuktosunoglu , Peter William Cook , Philip George Emma , Prabhakar N. Kudva , Stanley Everett Schuster
CPC分类号： H03K19/0016
摘要： Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so that the functions are energized or deenergized in a control sequence such that the functions where the data is resident are energized and at least one of the other functions is not energized.
摘要翻译： 泄漏电流控制装置包括在序列中执行功能的数据路径中具有一个或多个功能的电路。 每个功能具有功率降低逻辑以激励每个相应的功能。 泄漏控制电路与功率降低逻辑相互作用，使得功能在控制序列中被激励或断电，使得数据驻留的功能被激励，并且其他功能中的至少一个没有通电。
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9.发明授权Hardware execution driven application level derating calculation for soft error rate analysis 有权软件错误率分析的硬件执行驱动应用级降额计算公开(公告)号：US08949101B2
公开(公告)日：2015-02-03
申请号：US13271827
申请日：2011-10-12
IPC分类号： G01R31/3181 , G06F17/50 , G01R31/3183
CPC分类号： G01R31/31816 , G01R31/318357 , G06F17/5022
摘要： Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.
摘要翻译： 提供了用于预测软错误对集成电路器件设计的影响的机制。 数据处理系统被配置为实现统一的降额工具，其包括用于生成机器降额信息的机器降额前端引擎和用于生成应用降额信息的应用降级前端引擎用于集成电路器件设计。 机器降额前端引擎执行集成电路设备设计的仿真以生成机器降额信息。 应用降级前端引擎在架构上与集成电路设备设计类似的现有硬件上执行应用程序工作负载，并在执行应用程序工作负载期间将故障注入到现有硬件中，以生成应用程序降级信息。 机器降额信息与应用降级信息组合以产生用于集成电路设备设计的至少一个软错误率值。
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公开(公告)号：US08091050B2
公开(公告)日：2012-01-03
申请号：US12243427
申请日：2008-10-01
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.
摘要翻译： 提供了对软错误的系统级别影响进行建模的机制。 提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。 通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。 在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档 设计。 基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。
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