公开(公告)号：US07023929B2

公开(公告)日：2006-04-04

申请号：US10191994

申请日：2002-07-10

Applicant: Fernando A. Mujica ,  Udayan Dasgupta ,  Mangesh Sadafale ,  Sandeep Oswal ,  Prakash Easwaran

Inventor： Fernando A. Mujica ,  Udayan Dasgupta ,  Mangesh Sadafale ,  Sandeep Oswal ,  Prakash Easwaran

IPC: H04K1/10

CPC classification number: H04L27/367 ,  H04L27/2626

Abstract: A method of providing an improved transfer function for a Discrete Multitone (DMT) type modulation transmitter with digital filtering after modulation followed by digital to analog converter and analog filtering is provided by sending a test signal to said transmitter and measuring the results of the test signal to determine the transfer function. The inverse of the transfer function that needs to be compensated is determined and the inverse of transfer function to be compensated is truncated to the region of interest (H2). The desired band split component of pre-compensation filter is designed (H3). The desired target frequency response of the pre-compensation filter is determined by H4=H2*H3 where H4 is the multiplication of H2 and H3 Given the target frequency response in H4 Hermetian symmetry is imposed on the frequency response. The inverse Fourier transform (IFFT) is taken to generate a time domain filter, h5. The characteristic of this filter is added at the digital filtering after modulation.

Abstract translation: 通过向所述发射机发送测试信号并测量测试信号的结果，提供一种为调制后的数字滤波后的数模转换器和模拟滤波器为离散多音（DMT）型调制发射机提供改进的传递函数的方法 确定传递函数。 确定需要补偿的传递函数的逆，并且要补偿的传递函数的逆被截断到感兴趣的区域（H 2> 2）。 设计了预补偿滤波器的期望频带分离分量（H 3 3 3）。 预补偿滤波器的期望目标频率响应由H 4 = H 2 / H 3 3 H 3确定，其中H 4 < 假定在H 4中的目标频率响应，Hermetian对称性被施加在频率响应上，则/ SUB>是H 2 2和H 3 3的乘法。 采用逆傅里叶变换（IFFT）来产生时域滤波器h 5。 该滤波器的特性在调制后的数字滤波中相加。

公开(公告)号：US06831975B1

公开(公告)日：2004-12-14

申请号：US09661629

申请日：2000-09-13

Applicant: Prakash Easwaran ,  Sandeep Oswal

Inventor： Prakash Easwaran ,  Sandeep Oswal

IPC: H04M100

CPC classification number: H04L27/0002 ,  H03H11/1217 ,  H03H11/1252 ,  H04L5/14 ,  H04L27/2647

Abstract: A cost-effective filter consuming low power and occupying minimal space. The filter may be used in a ADSL modem (or CPE) to filter the signal components other than the ADSL signals. A high pass filter first filters the low frequency components to attenuate (or remove) lower frequency components such as that caused by ADSL transmit echo signals and that used for voice transmission. The high pass filter may be modified by adding a few resistors to limit the voltages of the high frequency signals also. The output of the high pass filter is amplified and passed through a low pass filter to filter the high frequency components (HPNA included). Due to earlier filtering operation of the high pass filter, the signal can be amplified substantially before being sent to the low pass filter. The implementation of the low pass filter is simplified due to the prior amplification.

Abstract translation: 消耗低功耗且占用最小空间的成本效益过滤器。 该滤波器可用于ADSL调制解调器（或CPE）中以对除ADSL信号之外的信号分量进行滤波。 高通滤波器首先对低频分量进行滤波，以衰减（或去除）较低频率的分量，例如由ADSL发射回波信号和用于语音传输的频率成分。 高通滤波器可以通过添加几个电阻器来修改，以限制高频信号的电压。 高通滤波器的输出被放大并通过低通滤波器以过滤高频分量（包括HPNA）。 由于高通滤波器的较早的滤波操作，可以在发送到低通滤波器之前基本上放大该信号。 由于先前的放大，低通滤波器的实现被简化。

公开(公告)号：US06816004B2

公开(公告)日：2004-11-09

申请号：US10259287

申请日：2002-09-30

Applicant: Prakash Easwaran ,  Naom Chaplik ,  Sandeep Oswal

Inventor： Prakash Easwaran ,  Naom Chaplik ,  Sandeep Oswal

IPC: H03K500

CPC classification number: H03H11/1217 ,  H03H11/126 ,  H04L5/1461

Abstract: A filter circuit with two 2nd order stages cascaded in sequence. The first stage is implemented with high quality (Q) factor, and the second stage is implemented with a low Q factor and an imaginary zero. The first stage is designed to further eliminate the unwanted frequency components. The imaginary zero in the second stage eliminates the noise present in the output of the first stage due to the requirement of high Q in the first stage. Any additional noise introduced by the second stage is minimal due to the low Q of the second stage. Each stage may be implemented using only a single operational amplifier when the first stage generates a differential output signal.

公开(公告)号：US06642779B2

公开(公告)日：2003-11-04

申请号：US10080535

申请日：2002-02-25

Applicant: Prakash Easwaran ,  Sandeep Oswal ,  Naom Chaplik

Inventor： Prakash Easwaran ,  Sandeep Oswal ,  Naom Chaplik

IPC: H03B520

CPC classification number: H03H7/25 ,  H03J1/00

Abstract: A T-network containing three impedances is provided between two terminating ends connected to a non-fixed voltage level. Two impedances are connected in series between the two terminating ends. A third impedance is connected between the junction of the first two impedances and a fixed voltage. Switches may be used to trim the third impedance, thus obtaining a desired voltage between the two terminating ends. A terminal of any switches used for trimming can be connected to the fixed voltage node, thereby ensuring that the impedance introduced by the switches does not change substantially during different operating situations.

Abstract translation: 在连接到非固定电压电平的两个终端之间提供包含三个阻抗的T网络。 两个阻抗串联在两个端接端之间。 第三阻抗连接在前两个阻抗的结点和固定电压之间。 可以使用开关来修整第三阻抗，从而在两个端接端之间获得期望的电压。 用于修整的任何开关的端子可以连接到固定电压节点，从而确保在不同的操作情况下由开关引入的阻抗基本上没有变化。

公开(公告)号：US08878510B2

公开(公告)日：2014-11-04

申请号：US13472461

申请日：2012-05-15

Applicant: Prasun Kali Bhattacharyya ,  Prakash Easwaran

Inventor： Prasun Kali Bhattacharyya ,  Prakash Easwaran

IPC: G05F3/08

CPC classification number: G05F1/565 ,  G05F1/575

Abstract: A voltage regulator includes an amplifier, a first buffer and a second buffer. The amplifier is designed to generate an error voltage between a reference voltage and a voltage at an output node of the voltage regulator. The first buffer is coupled to receive the amplified error voltage and, in response, to drive a first pass transistor. The first buffer includes a non-linear resistance element. The resistance of the non-linear resistance element varies non-linearly with a load current drawn from the output node. The second buffer is coupled to receive the amplified error voltage, and in response, to drive a second pass transistor. The second buffer includes a linear resistance element. The resistance of the linear element is a constant. The use of the non-linear resistance element enables reduction in power consumption in the voltage regulator.

Abstract translation: 电压调节器包括放大器，第一缓冲器和第二缓冲器。 放大器设计用于在电压调节器的输出节点处产生参考电压和电压之间的误差电压。 第一缓冲器被耦合以接收放大的误差电压，并且作为响应来驱动第一传输晶体管。 第一缓冲器包括非线性电阻元件。 非线性电阻元件的电阻随从输出节点引出的负载电流而非线性变化。 第二缓冲器被耦合以接收放大的误差电压，并且响应于驱动第二传输晶体管。 第二缓冲器包括线性电阻元件。 线性元件的电阻是一个常数。 使用非线性电阻元件能够降低电压调节器的功耗。

公开(公告)号：US08242762B2

公开(公告)日：2012-08-14

申请号：US12436136

申请日：2009-05-06

Applicant: Hrishikesh Bhagwat ,  Rupak Ghayal ,  Saumitra Singh ,  Pawan Gupta ,  Prakash Easwaran

Inventor： Hrishikesh Bhagwat ,  Rupak Ghayal ,  Saumitra Singh ,  Pawan Gupta ,  Prakash Easwaran

IPC: G05F1/575

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage.

Abstract translation: 用于开关器件的瞬态恢复电路。 瞬态恢复电路包括检测电路，用于通过检测输出电压瞬变的速率来检测开关装置的输出电压中的快速瞬变; 所述开关装置的反馈环路中的辅助控制电路，用于通过在检测到所述快速瞬变时改变所述反馈回路的带宽来校正所述输出电压; 以及用于在校正输出电压之后将连续导通模式中的反馈回路初始化为期望工作点的初始化电路。

公开(公告)号：US08049472B2

公开(公告)日：2011-11-01

申请号：US12463388

申请日：2009-05-09

Applicant: Prakash Easwaran ,  Rupak Ghayal ,  Raghavendra Rao Haresamudram

Inventor： Prakash Easwaran ,  Rupak Ghayal ,  Raghavendra Rao Haresamudram

IPC: G05F1/577

CPC classification number: H02M3/158 ,  H02M2001/009

Abstract: Single inductor multiple output (SIMO) switching devices with efficient regulating circuits. The SIMO switching device includes a plurality of time division multiplexing (TDM) switches for switching current through an inductor of the SIMO switching device. The plurality of TDM switches produces a plurality of outputs. The SIMO switching device further includes an error calculation circuit operatively coupled to the plurality of outputs for determining a calculated error from the plurality of outputs; a time slot generation circuit for controlling the plurality of TDM switches according to the calculated error; and a pulse width modulation (PWM) control circuit operatively coupled to the time slot generation circuit for controlling a plurality of PWM switches of a switching stage of the SIMO switching device in a continuous conduction mode (CCM) of operation. The PWM switches are controlled according to the time slots generated by the time slot generation circuit.

Abstract translation: 具有高效调节电路的单电感多输出（SIMO）开关器件。 SIMO切换装置包括用于切换通过SIMO切换装置的电感器的电流的多个时分复用（TDM）开关。 多个TDM交换机产生多个输出。 SIMO切换装置还包括可操作地耦合到多个输出的误差计算电路，用于从多个输出中确定计算出的误差; 时隙生成电路，用于根据计算出的误差来控制多个TDM交换机; 以及可操作地耦合到所述时隙产生电路的脉冲宽度调制（PWM）控制电路，用于在连续导通模式（CCM）中控制所述SIMO开关器件的开关级的多个PWM开关。 PWM开关根据时隙发生电路产生的时隙进行控制。

公开(公告)号：US07570191B2

公开(公告)日：2009-08-04

申请号：US11760778

申请日：2007-06-10

Applicant: Prakash Easwaran ,  Prasun Kali Bhattacharya ,  Venkatesh Teeka Srinivasa Shetty

Inventor： Prakash Easwaran ,  Prasun Kali Bhattacharya ,  Venkatesh Teeka Srinivasa Shetty

IPC: H03M1/38

CPC classification number: H03M1/0604 ,  H03M1/168

Abstract: Methods and systems for designing a high resolution analog to digital converter (ADC) by eliminating the errors in the ADC stages. An error correction architecture and method eliminate the gain error and settling error of the residue amplifier in a pipelined ADC stage. A reference voltage error correction architecture and method eliminate the reference voltage error due to the sampling action in the ADC. The gain error correction method calculates the gain error using an error amplifier and eliminates the gain error at a later stage of the ADC. The reference voltage error correction method calculates the reference voltage error using an ideal reference voltage and corrects the error at a later stage of the ADC. Therefore, the constraints of gain and settling of the residue amplifier is significantly reduced.

Abstract translation: 通过消除ADC阶段的错误来设计高分辨率模数转换器（ADC）的方法和系统。 错误校正架构和方法消除了流水线ADC阶段的残差放大器的增益误差和稳定误差。 参考电压误差校正架构和方法消除了ADC中采样动作引起的参考电压误差。 增益误差校正方法使用误差放大器计算增益误差，消除ADC后期的增益误差。 参考电压误差校正方法使用理想的参考电压计算参考电压误差，并在ADC后期校正误差。 因此，残差放大器的增益和稳定的约束显着降低。

公开(公告)号：US20130021092A1

公开(公告)日：2013-01-24

申请号：US13009868

申请日：2011-01-20

Applicant: Prasun Kali BHATTACHARYYA ,  Sumanth Chakkirala ,  Prakash Easwaran

Inventor： Prasun Kali BHATTACHARYYA ,  Sumanth Chakkirala ,  Prakash Easwaran

IPC: H03K5/00

CPC classification number: H03H7/0153 ,  H03H7/06 ,  H03H11/12 ,  H03H2210/012 ,  H03H2210/028

Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.

Abstract translation: 超低截止频率滤波器。 滤波电路包括响应于输入信号和反馈信号的控制电路以产生控制信号。 滤波器电路包括耦合到控制电路的可控电阻器。 可控电阻响应于参考信号和控制信号以产生反馈信号。 滤波器电路包括耦合到控制电路和可控电阻器的反馈路径，以将来自可控电阻器的反馈信号耦合到控制电路，从而从输入信号和参考信号中的至少一个消除噪声，并且防止电压误差 在滤波电路中。

公开(公告)号：US20090295609A1

公开(公告)日：2009-12-03

申请号：US11760743

申请日：2007-06-09

Applicant: T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

Inventor： T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0641 ,  H03M1/12

Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Abstract translation: 一种降低模数转换器（ADC）功耗的系统和方法。 该方法包括以下步骤：从多个时钟相位的前一相位接收残留输出，其中多个时钟相位包括采样保持相位和用于分别对模拟输入信号进行采样和放大的放大相位，消除 当放大残留物输出时，负载对残留放大器的影响，以在放大阶段产生放大的残留输出，并且在取样和保持阶段中对放大的残留输出进行采样时，消除小的反馈因子的影响。 通过在采样保持阶段和放大阶段共享残留放大器上的负载而不是完全存在于任何一个时钟相位来实现功率优点。 本发明还提供了一种减少ADC中使用的比较器数量的方法。