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公开(公告)号：US20140062751A1
公开(公告)日：2014-03-06
申请号：US13599539
申请日：2012-08-30
Applicant: Venugopal Gopinathan , Udayan Dasgupta , Ganesan Thiagarajan
Inventor： Venugopal Gopinathan , Udayan Dasgupta , Ganesan Thiagarajan
IPC: H03M1/34
CPC classification number: H03M1/12 , H03M1/10 , H03M1/125 , H03M1/126 , H03M1/127 , H03M1/18 , H03M1/181
Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.
Abstract translation: 提供了一种装置。 比较电路被配置为接收模拟信号。 参考电路耦合到比较电路，并被配置为向比较电路提供多个参考信号。 A转换电路耦合到比较电路，并被配置为检测比较电路的输出的变化。 时间数字转换器（TDC）耦合到比较电路。 定时器耦合到比较电路。 速率控制电路耦合到转换电路。 输出电路耦合到速率控制电路和TDC，其中输出电路被配置为输出模拟信号的同步数字表示和模拟信号的异步数字表示中的至少一个。
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公开(公告)号：US20090175234A1
公开(公告)日：2009-07-09
申请号：US12350523
申请日：2009-01-08
Applicant: Udayan Dasgupta , Muhammad Zubair Ikram , David Patrick Magee
Inventor： Udayan Dasgupta , Muhammad Zubair Ikram , David Patrick Magee
CPC classification number: H04L27/2602 , H04B7/2656 , H04L5/005 , H04L27/2613
Abstract: A method of performing wireless communications. The method comprises, at a transmitting station, encoding a plurality of symbols into a frame. The method further comprises, from the transmitting station, transmitting the frame via a wireless communication to a receiving station. The frame comprises a plurality of sub-frames, wherein a first sub-frame in the plurality of sub-frames consists of a first number of symbols and a second sub-frame in the plurality of sub-frames consists of a second number of symbols. Finally, the first number differs from the second number.
Abstract translation: 一种执行无线通信的方法。 该方法包括在发送站将多个符号编码成帧。 该方法还包括从发送站经由无线通信将帧发送到接收站。 所述帧包括多个子帧，其中所述多个子帧中的第一子帧由所述多个子帧中的第一数量的符号和第二子帧组成，所述第二子帧由第二数量的符号 。 最后，第一个数字与第二个数字不同。
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公开(公告)号：US07496134B2
公开(公告)日：2009-02-24
申请号：US11043218
申请日：2005-01-26
Applicant: Arthur J. Redfern , Udayan Dasgupta
Inventor： Arthur J. Redfern , Udayan Dasgupta
CPC classification number: H04L27/2608 , H04B1/38
Abstract: An integrated circuit 18 is provided that includes a memory 32 and a memory modification component 33. The memory 32 maintains a bits count, a gain, and a tone order for each of a plurality of discrete multi-tone sub-channels. The memory modification component 33 operable to control an in-service modification of at least some of the bits count, the gain, and the tone order using a single bits, gains and tone order table.
Abstract translation: 提供了包括存储器32和存储器修改组件33的集成电路18.存储器32维持多个离散多音调子频道中的每一个的比特计数，增益和音调顺序。 存储器修改组件33可用于使用单个位，增益和音调顺序表来控制比特计数，增益和音调顺序中的至少一些的在职修改。
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4.发明授权Vector math instruction execution by DSP processor approximating division and complex number magnitude 有权DSP处理器的矢量数学指令执行近似分割和复数量级公开(公告)号：US09015452B2
公开(公告)日：2015-04-21
申请号：US12708180
申请日：2010-02-18
Applicant: Udayan Dasgupta
Inventor： Udayan Dasgupta
CPC classification number: G06F9/30014 , G06F7/4806 , G06F7/535 , G06F7/548 , G06F7/552 , G06F9/30036 , G06F9/30065 , G06F9/3887 , G06F9/3891 , G06F2207/3828 , G06F2207/5354 , G06F2207/5525
Abstract: A digital signal processor (DSP) includes an instruction fetch unit, an instruction decode unit, a register set and a plurality of work units in communication with the instruction decode unit. A first embodiment calculates two divisions on packed numerators and packed denominators. The DSP work units calculate indexes into a 1/d look-up table and make a final sign correction. A second embodiment calculates an approximation of a vector magnitude of a complex number x+jy. The approximation is based upon √(x2+y2)≈α*max(|x|, |y|)+β*min(|x|, |y|). The DSP work units calculate the absolute values, find the maxima and minima, and form the packed results of two vector magnitude calculations.
Abstract translation: 数字信号处理器（DSP）包括与指令解码单元通信的指令获取单元，指令解码单元，寄存器组和多个工作单元。 第一实施例计算包装分子和包装分母上的两个部分。 DSP工作单元将索引计算到1 / d查找表中，并进行最终符号校正。 第二实施例计算复数x + jy的矢量幅度的近似。 近似值基于√（x2 + y2）≈α* max（| x |，| y |）+＆bgr; * min（| x |，| y |）。 DSP工作单元计算绝对值，找到最大值和最小值，并形成两个矢量幅度计算的压缩结果。
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5.发明授权公开(公告)号：US08830106B2
公开(公告)日：2014-09-09
申请号：US13599491
申请日：2012-08-30
Applicant: Udayan Dasgupta , Ganesan Thiagarajan , Venugopal Gopinathan
Inventor： Udayan Dasgupta , Ganesan Thiagarajan , Venugopal Gopinathan
Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.
Abstract translation: 提供了一种方法。 接收模拟信号。 将模拟输入信号与第一和第二参考信号进行比较以产生第一比较结果，并且登记与第一比较结果对应的第一比较结果和第一时间戳。 从第一比较结果生成数字信号的第一部分。 调整第一和第二参考信号中的至少一个。 如果模拟信号在预定间隔内达到第一和第二参考信号中调整的一个，并且从第二比较结果产生数字信号的第二部分，则产生第二比较结果。
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Patent Agency Ranking
公开(公告)号：US08754797B2
公开(公告)日：2014-06-17
申请号：US13599539
申请日：2012-08-30
Applicant: Venugopal Gopinathan , Udayan Dasgupta , Ganesan Thiagarajan
Inventor： Venugopal Gopinathan , Udayan Dasgupta , Ganesan Thiagarajan
CPC classification number: H03M1/12 , H03M1/10 , H03M1/125 , H03M1/126 , H03M1/127 , H03M1/18 , H03M1/181
Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.
Abstract translation: 提供了一种装置。 比较电路被配置为接收模拟信号。 参考电路耦合到比较电路，并被配置为向比较电路提供多个参考信号。 A转换电路耦合到比较电路，并被配置为检测比较电路的输出的变化。 时间数字转换器（TDC）耦合到比较电路。 定时器耦合到比较电路。 速率控制电路耦合到转换电路。 输出电路耦合到速率控制电路和TDC，其中输出电路被配置为输出模拟信号的同步数字表示和模拟信号的异步数字表示中的至少一个。
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公开(公告)号：US20140062734A1
公开(公告)日：2014-03-06
申请号：US13599452
申请日：2012-08-30
Applicant: Ganesan Thiagarajan , Udayan Dasgupta , Venugopal Gopinathan
Inventor： Ganesan Thiagarajan , Udayan Dasgupta , Venugopal Gopinathan
IPC: H03M1/50
Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.
Abstract translation: 提供了一种方法。 接收模拟信号。 将模拟输入信号与第一和第二参考信号进行比较以产生第一比较结果，并且登记与第一比较结果对应的第一比较结果和第一时间戳。 从第一比较结果生成数字信号的第一部分。 如果比较结果在预定间隔内保持基本相同，则ADC能够在采样时刻产生第二比较结果。 产生对应于采样时刻的第二时间戳。 登记与第一比较结果相对应的第二比较结果和第二时间戳，并且从第二比较结果生成数字信号的第二部分。
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公开(公告)号：US20100211761A1
公开(公告)日：2010-08-19
申请号：US12708180
申请日：2010-02-18
Applicant: Udayan DASGUPTA
Inventor： Udayan DASGUPTA
CPC classification number: G06F9/30014 , G06F7/4806 , G06F7/535 , G06F7/548 , G06F7/552 , G06F9/30036 , G06F9/30065 , G06F9/3887 , G06F9/3891 , G06F2207/3828 , G06F2207/5354 , G06F2207/5525
Abstract: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. A vector math instruction decoded by the instruction decode unit causes input vectors and output vectors to be aligned with a maximum boundary of the register set and causes parallel operations by the work units.
Abstract translation: 根据至少一些实施例，数字信号处理器（DSP）包括与指令提取单元通信的指令提取单元和指令解码单元。 DSP还包括与指令解码单元通信的寄存器组和多个工作单元。 由指令解码单元解码的向量数学指令使得输入向量和输出向量与寄存器组的最大边界对齐，并且由工作单元引起并行操作。
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公开(公告)号：US07298207B2
公开(公告)日：2007-11-20
申请号：US10966981
申请日：2004-10-15
Applicant: Susan Yim , Udayan Dasgupta , Sandeep Oswal , Murtaza Ali
Inventor： Susan Yim , Udayan Dasgupta , Sandeep Oswal , Murtaza Ali
CPC classification number: H03G3/001 , H03G1/0088 , H03G3/3036
Abstract: Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.
Abstract translation: 公开了用于提供多级系统的自动增益控制的系统和方法。 一种方法可以包括定义至少一个适于至少一个参数的参数，其中最小化多个增益级中的每一个的硬件容量并减轻多级系统的部分变化。 选择用于基于多个级的相对噪声优势来训练多个级的顺序。 对于根据所选择的顺序选择的多个级的给定级，在给定级的多个增益设置上测量多级系统的输出信号。 基于相对于为给定阶段定义的至少一个参数的测量输出信号，配置多级系统的给定级的增益设置。 多个增益级可以包括串联连接的模拟均衡器以及可编程增益放大器。
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10.发明申请System and method for tone ordering in discrete multi-tone (DMT) modems 有权用于离散多音调（DMT）调制解调器中音调排序的系统和方法公开(公告)号：US20060062289A1
公开(公告)日：2006-03-23
申请号：US11233452
申请日：2005-09-22
Applicant: Channamallesh Hiremath , Udayan Dasgupta , Zigang Yang , Umashanker Iyer , Michael Locke
Inventor： Channamallesh Hiremath , Udayan Dasgupta , Zigang Yang , Umashanker Iyer , Michael Locke
CPC classification number: H04L5/006 , H04L1/0071 , H04L1/04 , H04L5/0007 , H04L5/0044 , H04L27/2647
Abstract: A system and method for reordering tones of a DMT signal within a communication system is described. Cross tone correlated noise in a received signal is identified and rearranged such that tones with correlated noise are spread out throughout the received signal before being processed by a decoder such as, Viterbi decoder. In an embodiment, two tones with the most correlated noise are placed at each end of the sequence of tones presented to the Viterbi decoder. In some embodiment, the tones with correlated noise can be spread such that two adjacent tones with correlated noise have a minimum distance of at least three tones between them at the input to the Viterbi decoder. In other embodiment, tones in the received signal can be processed in various kinds of interleavers for reordering according to the interleaver scheme.
Abstract translation: 描述了用于在通信系统内重新排序DMT信号的音调的系统和方法。 识别和重新排列接收信号中的交叉音相关噪声，使得具有相关噪声的音调在由诸如维特比解码器之类的解码器处理之前，在整个接收信号中被扩展。 在一个实施例中，具有最相关噪声的两个音调被放置在呈现给维特比解码器的音调序列的每一端。 在一些实施例中，可以扩展具有相关噪声的音调，使得具有相关噪声的两个相邻音调在维特比解码器的输入处具有至少三个音调的最小距离。 在其他实施例中，可以根据交织器方案在各种交织器中处理接收信号中的音调以进行重新排序。
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