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    Integrated circuit logic with self compensating block delays
    1.
    发明授权
    Integrated circuit logic with self compensating block delays 有权
    具有自补偿块延迟的集成电路逻辑

    公开(公告)号：US07084476B2

    公开(公告)日：2006-08-01

    申请号：US10787488

    申请日：2004-02-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  David S. Kung ,  Daniel L. Ostapko

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  David S. Kung ,  Daniel L. Ostapko

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0207 ,  H01L27/092

    摘要： An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

    摘要翻译： 一种包括至少一个组合逻辑路径的集成电路（IC）。 组合逻辑路径包括两种类型的逻辑块，其彼此补偿用于对单元晶体管的制造参数影响。 这两种类型可以是在接触间距处具有场效应晶体管（FET）栅极的密集电池，并且具有FET栅极的隔离电池宽于接触间距。 从被打印出焦点的FET栅极的密集单元延迟变化被隔离的单元延迟变化抵消。

    Integrated circuit logic with self compensating shapes
    2.
    发明授权
    Integrated circuit logic with self compensating shapes 有权
    具有自补偿形状的集成电路逻辑

    公开(公告)号：US07302671B2

    公开(公告)日：2007-11-27

    申请号：US11097552

    申请日：2005-04-01

    申请人： Fook-Luen Heng ,  Jin-Fuw Lee ,  Daniel L. Ostapko

    发明人： Fook-Luen Heng ,  Jin-Fuw Lee ,  Daniel L. Ostapko

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0207 ,  H01L27/092

    摘要： An integrated circuit (IC) including at least one combinational logic path. The features in the combinational logic path are self compensating for out-of-focus effects. In particular, field effect transistor (FET) gates may be iso-focally spaced such that the gate (critical dimension) may move with changing focus, but the gate length remains the same. Alternately, logic circuits in a path may self-compensate for focus effects on individual circuits.

    摘要翻译： 一种包括至少一个组合逻辑路径的集成电路（IC）。 组合逻辑路径中的特征是对于失焦效应的自我补偿。 特别地，场效应晶体管（FET）栅极可以是等焦点间隔开的，使得栅极（临界尺寸）可以随着焦点变化而移动，但是栅极长度保持相同。 或者，路径中的逻辑电路可以自我补偿各个电路上的聚焦效应。

    Partitioned mask layout
    3.
    发明授权
    Partitioned mask layout 失效
    分区面具布局

    公开(公告)号：US06383847B1

    公开(公告)日：2002-05-07

    申请号：US09699895

    申请日：2000-10-30

    申请人： Gary S. Ditlow ,  Fook-Luen Heng ,  Mark A. Lavin ,  Daniel L. Ostapko ,  Jung H. Yoon

    发明人： Gary S. Ditlow ,  Fook-Luen Heng ,  Mark A. Lavin ,  Daniel L. Ostapko ,  Jung H. Yoon

    IPC分类号： H01L2182

    CPC分类号： G03F1/00

    摘要： In connection with the manufacture of chips having partitioned logic, a partitioned mask layout approach. This approach provides the chip exposure pattern as a set of partitions corresponding to macros or core functions and also handles glue logic and interconnect. A result of this approach is a simplified, cost-effective process that does not defer customization to other, potentially more time-consuming and inefficient tasks.

    摘要翻译： 关于具有分割逻辑的芯片的制造，分割的掩模布局方法。 这种方法将芯片曝光模式提供为与宏或核心功能相对应的一组分区，并且还处理胶合逻辑和互连。 这种方法的结果是简化的，具有成本效益的过程，不会将定制推迟到其他可能更耗时和低效的任务。

    Lithographic process window optimization under complex constraints on edge placement
    4.
    发明授权
    Lithographic process window optimization under complex constraints on edge placement 有权
    边缘放置复杂约束下的平版印刷工艺窗口优化

    公开(公告)号：US07269817B2

    公开(公告)日：2007-09-11

    申请号：US10776901

    申请日：2004-02-10

    申请人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Daniel L. Ostapko ,  Alan E. Rosenbluth ,  Nakgeuon Seong

    发明人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Daniel L. Ostapko ,  Alan E. Rosenbluth ,  Nakgeuon Seong

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules. Pursuant to the method and system, lithographic capability and process windows are maximized to satisfy local circuit requirements and in order to achieve a maximally efficient layout. In this connection, there is employed a method utilizing a generalized lithographic process window as a measure when layout optimization is extended to a degree beyond that achieved by the simple fixed design rules which are applied to the design rules obtained is the advantage that a lithographic process window is determined purely through the calculation of image intensities and slopes, and as a result, the method can be quite rapid in application because it is possible to take advantage of known methods for rapid calculation of image intensity, and because there is obviated the need for geometrical shape processing during optimization.

    摘要翻译： 一种用于相对于光刻工艺窗口的布局优化的方法和系统，其有助于光刻约束被非局部化，以便赋予给定电路打印超过可以​​用常规简化设计规则达到的过程窗口的处理窗口的能力。 根据方法和系统，光刻能力和工艺窗口最大化，以满足局部电路要求，并实现最大限度的高效布局。 在这方面，采用一种利用广义平版印刷工艺窗口作为测量的方法，当布局优化扩展到超过通过简单的固定设计规则实现的程度时，应用于所获得的设计规则是光刻工艺的优点 通过计算图像强度和斜率来确定窗口，结果，该方法在应用中可以相当快速，因为可以利用已知的方法来快速计算图像强度，并且因为不需要 用于优化期间的几何形状处理。

    Method of IC fabrication, IC mask fabrication and program product therefor
    5.
    发明授权
    Method of IC fabrication, IC mask fabrication and program product therefor 失效
    IC制造方法，IC掩模制造及其程序产品

    公开(公告)号：US07353492B2

    公开(公告)日：2008-04-01

    申请号：US11043482

    申请日：2005-01-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  Mark A. Lavin

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  Mark A. Lavin

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.

    摘要翻译： 一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。 单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。 具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。 只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

    Method of IC fabrication, IC mask fabrication and program product therefor
    6.
    发明申请
    Method of IC fabrication, IC mask fabrication and program product therefor 失效
    IC制造方法，IC掩模制造及其程序产品

    公开(公告)号：US20050193363A1

    公开(公告)日：2005-09-01

    申请号：US11043482

    申请日：2005-01-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    IPC分类号： G03F1/14 ,  G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.

    摘要翻译： 一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。 单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。 具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。 只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

    Integrated circuit logic with self compensating block delays
    7.
    发明申请
    Integrated circuit logic with self compensating block delays 有权
    具有自补偿块延迟的集成电路逻辑

    公开(公告)号：US20050189604A1

    公开(公告)日：2005-09-01

    申请号：US10787488

    申请日：2004-02-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  David Kung ,  Daniel Ostapko

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  David Kung ,  Daniel Ostapko

    IPC分类号： H01L27/118 ,  G06F17/50 ,  H01L21/82 ,  H01L27/02 ,  H01L27/092 ,  H01L29/00 ,  H03K5/13

    CPC分类号： H01L27/0207 ,  H01L27/092

    摘要： An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

    摘要翻译： 一种包括至少一个组合逻辑路径的集成电路（IC）。 组合逻辑路径包括两种类型的逻辑块，其彼此补偿用于对单元晶体管的制造参数影响。 这两种类型可以是在接触间距处具有场效应晶体管（FET）栅极的密集电池，并且具有FET栅极的隔离电池宽于接触间距。 从被打印出焦点的FET栅极的密集单元延迟变化被隔离的单元延迟变化抵消。

    Spatial correlation-based estimation of yield of integrated circuits
    9.
    发明授权
    Spatial correlation-based estimation of yield of integrated circuits 有权
    基于空间相关的集成电路产量估计

    公开(公告)号：US08276102B2

    公开(公告)日：2012-09-25

    申请号：US12718567

    申请日：2010-03-05

    申请人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

    发明人： Fook-Luen Heng ,  Alexey Y. Lvov ,  Amith Singhee

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50

    摘要： Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2t×2s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

    摘要翻译： 提供了用于估计诸如大规模集成（VLSI）设计的集成电路设计的产量的技术。 一方面，用于确定VLSI查询设计的故障概率的方法包括以下步骤。 构建了一个Voronoi图，它包含一组代表设计的形状。 Voronoi图被转换为包括2t×2s矩形单元格的矩形网格，其中选择t和s，使得一个矩形单元格包含约一个至约五个Voronoi单元。 为网格中的每个单元格计算故障概率。 网格中的单元格成对合并。 重新计算合并的单元的故障概率，这说明了单元之间的空间相关性。 成对合并和重新计算步骤执行s + t次以确定设计失败的概率。