公开(公告)号：US20140032819A1

公开(公告)日：2014-01-30

申请号：US13561306

申请日：2012-07-30

申请人： Tu To Dang ,  Juan Q. Hernandez ,  Sumeet Kochar ,  Jung H. Yoon

发明人： Tu To Dang ,  Juan Q. Hernandez ,  Sumeet Kochar ,  Jung H. Yoon

IPC分类号： G06F12/02

CPC分类号： G06F11/2284 ,  G06F1/3225 ,  G06F11/3037 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3476 ,  G06F12/0246 ,  G06F2201/88 ,  G11C7/20 ,  G11C11/1673 ,  G11C11/4072 ,  G11C2029/0407 ,  G11C2029/4402 ,  Y02D10/34

摘要： An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.

摘要翻译： 提供了一种用于确定新安装到计算机系统中的存储器件的通电小时偏移的方法，其从当前的电源开启时间值中减去存储器件的当前通电时间计数 的电源，其向计算机系统内的存储器装置提供操作电力。 响应于计算机系统断电，通过从计算机系统电源的当前通电时间值中减去存储器的电源开启时间偏移来确定存储器件的累积上电时间。 所确定的上电时间偏移和累积的上电时间值被保存到存储器装置的电可擦除可编程只读存储器的一个或多个指定字节中，该可擦除可编程只读存储器可用于存储器控制器的数据存储 并且其中存储在其中的数据在操作功率丢失到存储器设备，存储器控制器或计算机系统之后持续。

公开(公告)号：US20080116571A1

公开(公告)日：2008-05-22

申请号：US11604152

申请日：2006-11-22

申请人： Hien P. Dang ,  Vinod Kamath ,  Vijayeshwar D. Khanna ,  Gerard McVicker ,  Sri M. Sri-Jayantha ,  Jung H. Yoon

发明人： Hien P. Dang ,  Vinod Kamath ,  Vijayeshwar D. Khanna ,  Gerard McVicker ,  Sri M. Sri-Jayantha ,  Jung H. Yoon

IPC分类号： H01L23/467

CPC分类号： H01L23/4093 ,  H01L23/3672 ,  H01L23/467 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottom area of the structure.

摘要翻译： 用于直列芯片模块的弹簧状冷却结构由具有前侧和后侧的导热材料的连续片材形成，所述片材以基本上以一百八十度的角度折叠，其中长度 的结构基本上与直列芯片模块的长度相关，并且该结构的宽度比直列芯片模块的宽度宽，使得该结构适合于并且基本上围绕在线芯片模块; 在结构的左侧，右侧和底部的开口，用于容易地从线内芯片模块固定和移除结构; 顶部，其包括顶部表面，所述顶部表面设置在所述直列芯片模块的顶部上，当固定到所述在线芯片模块时，并且包括从所述直列芯片模块向外扩张的成角度的表面， 顶面 中心水平部分; 中心水平部分和多个芯片之间的间隙; 和结构的扩口底部区域。

公开(公告)号：US07612446B2

公开(公告)日：2009-11-03

申请号：US11604152

申请日：2006-11-22

申请人： Hien P. Dang ,  Vinod Kamath ,  Vijayeshwar D. Khanna ,  Gerard McVicker ,  Sri M. Sri-Jayantha ,  Jung H. Yoon

发明人： Hien P. Dang ,  Vinod Kamath ,  Vijayeshwar D. Khanna ,  Gerard McVicker ,  Sri M. Sri-Jayantha ,  Jung H. Yoon

IPC分类号： H01L23/34 ,  H05K7/20 ,  H01L21/00 ,  F28F7/00

CPC分类号： H01L23/4093 ,  H01L23/3672 ,  H01L23/467 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottom area of the structure.

摘要翻译： 用于直列芯片模块的弹簧状冷却结构由具有前侧和后侧的导热材料的连续片材形成，所述片材以基本上以一百八十度的角度折叠，其中长度 的结构基本上与直列芯片模块的长度相关，并且该结构的宽度比直列芯片模块的宽度宽，使得该结构适合于并且基本上围绕在线芯片模块; 在结构的左侧，右侧和底部的开口，用于容易地从线内芯片模块固定和移除结构; 顶部，其包括顶部表面，所述顶部表面设置在所述直列芯片模块的顶部上，当固定到所述在线芯片模块时，并且包括从所述直列芯片模块向外扩张的成角度的表面， 顶面 中心水平部分; 中心水平部分和多个芯片之间的间隙; 和结构的扩口底部区域。

公开(公告)号：US5219788A

公开(公告)日：1993-06-15

申请号：US661561

申请日：1991-02-25

申请人： John R. Abernathey ,  Timothy H. Daubenspeck ,  Stephen E. Luce ,  Denis J. Poley ,  Rosemary A. Previti-Kelly ,  Gary P. Viens ,  Jung H. Yoon

发明人： John R. Abernathey ,  Timothy H. Daubenspeck ,  Stephen E. Luce ,  Denis J. Poley ,  Rosemary A. Previti-Kelly ,  Gary P. Viens ,  Jung H. Yoon

IPC分类号： G03F7/11 ,  G03F7/09 ,  G03F7/36 ,  H01L21/027

CPC分类号： G03F7/091 ,  Y10S438/902 ,  Y10S438/95 ,  Y10S438/952

摘要： A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO.sub.2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

公开(公告)号：US08990479B2

公开(公告)日：2015-03-24

申请号：US13561306

申请日：2012-07-30

申请人： Tu To Dang ,  Juan Q. Hernandez ,  Sumeet Kochar ,  Jung H. Yoon

发明人： Tu To Dang ,  Juan Q. Hernandez ,  Sumeet Kochar ,  Jung H. Yoon

IPC分类号： G06F12/00

CPC分类号： G06F11/2284 ,  G06F1/3225 ,  G06F11/3037 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3476 ,  G06F12/0246 ,  G06F2201/88 ,  G11C7/20 ,  G11C11/1673 ,  G11C11/4072 ,  G11C2029/0407 ,  G11C2029/4402 ,  Y02D10/34

摘要： An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system.

摘要翻译： 提供了一种用于确定新安装到计算机系统中的存储器件的通电小时偏移的方法，其从当前的电源开启时间值中减去存储器件的当前通电时间计数 的电源，其向计算机系统内的存储器装置提供操作电力。 响应于计算机系统断电，通过从计算机系统电源的当前通电时间值中减去存储器的电源开启时间偏移来确定存储器件的累积上电时间。 所确定的上电时间偏移和累积的上电时间值被保存到存储器装置的电可擦除可编程只读存储器的一个或多个指定字节中，该可擦除可编程只读存储器可用于存储器控制器的数据存储 并且其中存储在其中的数据在操作功率丢失到存储器设备，存储器控制器或计算机系统之后持续。

公开(公告)号：US5229257A

公开(公告)日：1993-07-20

申请号：US516415

申请日：1990-04-30

申请人： John E. Cronin ,  Carter W. Kaanta ,  Pei-Ing P. Lee ,  Rosemary A. Previti-Kelly ,  James G. Ryan ,  Jung H. Yoon

发明人： John E. Cronin ,  Carter W. Kaanta ,  Pei-Ing P. Lee ,  Rosemary A. Previti-Kelly ,  James G. Ryan ,  Jung H. Yoon

IPC分类号： C08G73/10 ,  G03F7/038 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/46

CPC分类号： H01L21/76828 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L23/5226 ,  H05K3/0023 ,  H05K3/467 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K2201/0154 ,  H05K3/045 ,  H05K3/107 ,  H05K3/465

摘要： Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate having a conductor pattern. The insulator layers, each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

公开(公告)号：US06869899B2

公开(公告)日：2005-03-22

申请号：US09902727

申请日：2001-07-12

申请人： Arpan P. Mahorowala ,  Maheswaran Surendra ,  Jung H. Yoon ,  Ying Zhang

发明人： Arpan P. Mahorowala ,  Maheswaran Surendra ,  Jung H. Yoon ,  Ying Zhang

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/00

CPC分类号： H01L21/28123 ,  H01L21/32137 ,  H01L21/32139 ,  Y10S438/945 ,  Y10S438/947 ,  Y10S438/949 ,  Y10S438/95

摘要： The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or next generation lithography techniques. The invention relates more particularly, but not by way of limitation, to lateral trimming of photoresist images.

摘要翻译： 本发明一般涉及非常小的特征的平版印刷图案。 特别地，本发明一般涉及使用常规光刻或下一代光刻技术小于光刻定义的半导体电路特征的图案化。 本发明更具体地但非限制性地涉及光致抗蚀剂图像的横向修整。

公开(公告)号：US06383847B1

公开(公告)日：2002-05-07

申请号：US09699895

申请日：2000-10-30

申请人： Gary S. Ditlow ,  Fook-Luen Heng ,  Mark A. Lavin ,  Daniel L. Ostapko ,  Jung H. Yoon

发明人： Gary S. Ditlow ,  Fook-Luen Heng ,  Mark A. Lavin ,  Daniel L. Ostapko ,  Jung H. Yoon

IPC分类号： H01L2182

CPC分类号： G03F1/00

摘要： In connection with the manufacture of chips having partitioned logic, a partitioned mask layout approach. This approach provides the chip exposure pattern as a set of partitions corresponding to macros or core functions and also handles glue logic and interconnect. A result of this approach is a simplified, cost-effective process that does not defer customization to other, potentially more time-consuming and inefficient tasks.

摘要翻译： 关于具有分割逻辑的芯片的制造，分割的掩模布局方法。 这种方法将芯片曝光模式提供为与宏或核心功能相对应的一组分区，并且还处理胶合逻辑和互连。 这种方法的结果是简化的，具有成本效益的过程，不会将定制推迟到其他可能更耗时和低效的任务。