公开(公告)号：US20140079215A1

公开(公告)日：2014-03-20

申请号：US14024424

申请日：2013-09-11

Applicant: QUALCOMM Incorporated

Inventor： Justin Y. Wei ,  Antoine Dambre ,  Christopher Ahn ,  Gurvinder Singh Chhabra

IPC: H04L9/08

CPC classification number: H04L9/0816 ,  H04L9/0662 ,  H04L9/0668 ,  H04L2209/12 ,  H04L2209/122

Abstract: Application of a ZUC cryptographic functions in wireless communication includes receiving a data stream at the wireless communication apparatus and applying the ZUC cryptographic function to the data stream. The ZUC cryptographic function includes generating at least one multi-byte pseudo-random number that provides an index to one of a plurality of substitution boxes. Each of the substitution boxes is further based on one or more normative substitution boxes. The ZUC cryptographic function further includes retrieving a value from each of the substitution boxes using each byte of the multi-byte pseudo-random number, assembling the retrieved values into at least one substituted values, and generating at least one key value based on the substituted values, wherein the key value is used in applying the ZUC cryptographic function to the data stream. The method also includes processing the data stream after application of the ZUC cryptographic function.

Abstract translation: ZUC加密功能在无线通信中的应用包括在无线通信装置处接收数据流并将ZUC加密功能应用于数据流。 ZUC加密功能包括生成至少一个多字节伪随机数，其向多个取代框之一提供索引。 每个替代框进一步基于一个或多个规范性替代框。 ZUC加密功能还包括使用多字节伪随机数的每个字节从每个替换盒中检索一个值，将检索到的值组装成至少一个替换值，并且基于取代的值生成至少一个密钥值 值，其中所述键值用于将ZUC加密功能应用于所述数据流。 该方法还包括在应用ZUC加密功能之后处理数据流。

公开(公告)号：US20130283280A1

公开(公告)日：2013-10-24

申请号：US13762587

申请日：2013-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： Steven D. Cheng ,  Gurvinder Singh Chhabra

IPC: G06F9/48

CPC classification number: G06F9/4893 ,  G06F9/5094 ,  H04W52/029 ,  Y02D10/22 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146

Abstract: Aspects of the disclosure generally relate to methods and apparatus for wireless communication. In an aspect, a method for dynamically processing data on interleaved multithreaded (MT) systems is provided. The method generally includes monitoring loading on one or more active processor threads, determining whether to remove a task or create an additional task based on the monitored loading of the one or more active processor threads and a number of tasks running on one or more of the one or more active processor threads, and if a determination is made to remove a task or create an additional task, distributing the resulting tasks among one or more available processor threads.

Abstract translation: 本公开的方面通常涉及用于无线通信的方法和装置。 在一方面，提供了一种用于动态处理交错多线程（MT）系统上的数据的方法。 该方法通常包括在一个或多个活动处理器线程上监视加载，基于所监视的一个或多个活动处理器线程的负载来确定是否去除任务或创建附加任务，以及在一个或多个活动处理器线程上运行的多个任务 一个或多个活动处理器线程，并且如果确定移除任务或创建附加任务，则在一个或多个可用处理器线程之间分配所生成的任务。

公开(公告)号：US11782762B2

公开(公告)日：2023-10-10

申请号：US16801776

申请日：2020-02-26

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Sundeep Kushwaha ,  Harsha Gordhan Jagasia ,  Christopher Ahn ,  Gurvinder Singh Chhabra ,  Nieyan Geng ,  Maksim Krasnyanskiy ,  Unni Prasad

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F12/0806

CPC classification number: G06F9/5016 ,  G06F9/4806 ,  G06F9/5022 ,  G06F12/0806 ,  G06F2209/481 ,  G06F2209/503 ,  G06F2212/1021

Abstract: A method of managing a stack includes detecting, by a stack manager of a processor, that a size of a frame to be allocated exceeds available space of a first stack. The first stack is used by a particular task executing at the processor. The method also includes designating a second stack for use by the particular task. The method further includes copying metadata associated with the first stack to the second stack. The metadata enables the stack manager to transition from the second stack to the first stack upon detection that the second stack is no longer in use by the particular task. The method also includes allocating the frame in the second stack.

公开(公告)号：US11416236B2

公开(公告)日：2022-08-16

申请号：US16028321

申请日：2018-07-05

Applicant: QUALCOMM Incorporated

Inventor： Nieyan Geng ,  Gurvinder Singh Chhabra ,  Chenyang Liu ,  Chuguang He

IPC: G06F8/65 ,  H03M7/30 ,  H04L67/00 ,  G06F8/654 ,  H04L69/04 ,  G06F8/658

Abstract: Embodiments of the present disclosure include systems and methods for efficient over-the-air updating of firmware having compressed and uncompressed segments. The method includes receiving a first update to the firmware via a radio, wherein the first update includes a first uncompressed segment and a first compressed segment, receiving a second update to the firmware, wherein the second update corresponds to the first compressed segment, compressing the second update to generate a compressed second update, applying the first update to the firmware, and applying the compressed second update to the firmware to generate an updated firmware.

公开(公告)号：US20180217930A1

公开(公告)日：2018-08-02

申请号：US15420667

申请日：2017-01-31

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F12/0808 ,  G06F12/128

CPC classification number: G06F12/0808 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/128 ,  G06F2212/401 ,  G06F2212/621 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: Aspects disclosed involve reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur. A processor-based system is provided that includes a cache memory and a compression memory system. When a cache entry is evicted from the cache memory, cache data and a virtual address associated with the evicted cache entry are provided to the compression memory system. The compression memory system reads metadata associated with the virtual address of the evicted cache entry to determine the physical address in the compression memory system mapped to the evicted cache entry. If the metadata is not available, the compression memory system stores the evicted cache data at a new, available physical address in the compression memory system without waiting for the metadata. Thus, buffering of the evicted cache data to avoid or reduce stalling write operations is not necessary.

公开(公告)号：US20140079220A1

公开(公告)日：2014-03-20

申请号：US14024444

申请日：2013-09-11

Applicant: QUALCOMM Incorporated

Inventor： Justin Y. Wei ,  Antoine Dambre ,  Christopher Ahn ,  Gurvinder Singh Chhabra

IPC: H04W12/04

CPC classification number: H04W12/04 ,  H04L9/0656 ,  H04L9/0668 ,  H04L9/0891 ,  H04L49/90 ,  H04L63/0457 ,  H04L63/062 ,  H04L63/08 ,  H04L63/162 ,  H04L2209/20 ,  H04L2209/80 ,  H04W12/02 ,  Y02D70/122 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/146

Abstract: Enhanced cryptographic techniques are provided which facilitate higher data rates in a wireless communication system. In one aspect, improvements to the ZUC algorithm are disclosed which can reduce the number of logical operations involved key stream generation, reduce computational burden on a mobile device implementing ZUC, and extend battery life. The disclosed techniques include, for instance, receiving, at a wireless communication apparatus, a data stream having data packets for ciphering or deciphering. The wireless apparatus can generate a cipher key for the cryptographic function, determine a starting address of a first data packet in the data stream and shift the cipher key to align with the starting address of the first data packet. Once aligned, the processing apparatus applies the cryptographic function to a first block of the first data packet using the shifted cipher key and manages a remaining portion of the cipher key to handle arbitrarily aligned data across multiple packets

Abstract translation: 提供了增强的加密技术，其有助于在无线通信系统中更高的数据速率。 在一方面，公开了对ZUC算法的改进，其可以减少涉及密钥流生成的逻辑操作的数量，减少实现ZUC的移动设备的计算负担，并延长电池寿命。 所公开的技术包括例如在无线通信装置处接收具有用于加密或解密的数据分组的数据流。 无线装置可以生成用于加密功能的加密密钥，确定数据流中的第一数据分组的起始地址，并移位密码以与第一数据分组的起始地址一致。 一旦对准，处理装置使用移位的加密密钥将加密功能应用于第一数据分组的第一块，并且管理密码密钥的剩余部分以跨多个分组处理任意对齐的数据

公开(公告)号：US11868244B2

公开(公告)日：2024-01-09

申请号：US17572471

申请日：2022-01-10

Applicant: QUALCOMM Incorporated

Inventor： Norris Geng ,  Richard Senior ,  Gurvinder Singh Chhabra ,  Kan Wang

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/401

Abstract: A compressed memory system of a processor-based system includes a memory partitioning circuit for partitioning a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high priority data region and a second cache line from a low priority data region. The system also includes a compression circuit for compressing the cache lines to obtain a first and a second compressed cache line. The system also includes a cache line packing circuit for packing the compressed cache lines such that the first compressed cache line is written to a first predetermined portion and the second cache line or a portion of the second compressed cache line is written to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.

公开(公告)号：US10678705B2

公开(公告)日：2020-06-09

申请号：US16130069

申请日：2018-09-13

Applicant: QUALCOMM Incorporated

Inventor： Nieyan Geng ,  Gurvinder Singh Chhabra ,  Caoye Shen ,  Samir Thakkar ,  Chuguang He

IPC: G06F12/10 ,  G06F12/109 ,  G06F9/50 ,  G06F9/4401 ,  G06F12/02 ,  G06F9/455

Abstract: Various embodiments include methods and devices for implementing external paging and swapping for dynamic modules on a computing device. Embodiments may include assigning static virtual addresses to a base image and dynamic modules of a static image of firmware of the computing device from a virtual address space for the static image, decompose static image into the base image and the dynamic modules, load the base image to an execution memory during a boot time from first partition of a storage memory, reserve a swap pool in the execution memory during the boot time, and load a dynamic module of the dynamic modules to the swap pool from a second partition of storage memory during a run time.

公开(公告)号：US10482021B2

公开(公告)日：2019-11-19

申请号：US15193001

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Richard Senior ,  Anand Janakiraman

IPC: G06F12/0871 ,  G06F12/0868

Abstract: In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in memory space left by the compression of high priority lines. The space left by the high priority lines and hence the low priority lines themselves are managed through pointers also stored in memory. In this manner, low priority lines contents can be moved to different memory locations as needed. The efficiency of higher priority compressed memory accesses is improved by removing the need for indirection otherwise required to find and access compressed memory lines, this is especially advantageous for immutable compressed contents. The use of pointers for low priority is advantageous due to the full flexibility of placement, especially for mutable compressed contents that may need movement within memory for instance as it changes in size over time.

公开(公告)号：US10169246B2

公开(公告)日：2019-01-01

申请号：US15592611

申请日：2017-05-11

Applicant: QUALCOMM Incorporated

Inventor： Richard Senior ,  Christopher Edward Koob ,  Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela ,  Nieyan Geng ,  Raghuveer Raghavendra ,  Christopher Porter ,  Anand Janakiraman

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1036

Abstract: Reducing metadata size in compressed memory systems of processor-based systems is disclosed. In one aspect, a compressed memory system provides 2N compressed data regions, corresponding 2N sets of free memory lists, and a metadata circuit. The metadata circuit associates virtual addresses with abbreviated physical addresses, which omit N upper bits of corresponding full physical addresses, of memory blocks of the 2N compressed data regions. A compression circuit of the compressed memory system receives a memory access request including a virtual address, and selects one of the 2N compressed data regions and one of the 2N sets of free memory lists based on a modulus of the virtual address and 2N. The compression circuit retrieves an abbreviated physical address corresponding to the virtual address from the metadata circuit, and performs a memory access operation on a memory block associated with the abbreviated physical address in the selected compressed data region.