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1.发明授权公开(公告)号：US09160357B1
公开(公告)日：2015-10-13
申请号：US14609383
申请日：2015-01-29
Applicant: QUALCOMM Incorporated
Inventor： Tongyu Song , Derui Kong
CPC classification number: H03M1/1047 , H03M1/1057 , H03M1/68 , H03M1/742
Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error.
Abstract translation: 在本公开的一方面，提供了一种用于校准DAC的方法和装置。 该装置校准第一DAC元件，提供由校准导致的剩余电流误差，剩余电流误差是第一DAC元件的校准电流源与参考电流源之间的差，存储校准的第一个 DAC元件，其使用至少第一和第二存储元件耦合到差分放大器，并且使用所存储的剩余电流误差来校准第二DAC元件。
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公开(公告)号：US20140240152A1
公开(公告)日：2014-08-28
申请号：US13779122
申请日：2013-02-27
Applicant: QUALCOMM INCORPORATED
Inventor： Tongyu Song
IPC: H03M1/10
CPC classification number: H03M1/1009 , H03M1/1061 , H03M1/742
Abstract: Circuits, methods, non-transitory storage media can be configured to reduce calibration errors in a signal converter. A digital-to-analog converter can include a calibration circuit configured to calibrate a digital-to-analog converter (DAC) bit element using a residual error from a previously calibrated digital-to-analog converter (DAC) bit element. The residual error can be stored in memory.
Abstract translation: 电路，方法，非暂时性存储介质可以配置为减少信号转换器中的校准误差。 数模转换器可以包括被配置为使用来自先前校准的数模转换器（DAC）位元素的残差来校准数模转换器（DAC）位元件的校准电路。 剩余错误可以存储在内存中。
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公开(公告)号：US09379727B1
公开(公告)日：2016-06-28
申请号：US14628996
申请日：2015-02-23
Applicant: QUALCOMM Incorporated
Inventor： Dongwon Seo , Yang You , Honghao Ji , Tongyu Song , Ganesh Saripalli , Shahin Mehdizad Taleie
IPC: H03M1/06 , H03M1/70 , H04B1/04 , G05F3/18 , G05F1/56 , H03M1/00 , H03M1/74 , G05F1/575 , H02M3/156
CPC classification number: H03M1/0604 , G05F1/56 , G05F1/575 , G05F3/18 , H02M3/156 , H03F3/24 , H03M1/00 , H03M1/70 , H03M1/747 , H04B1/0475 , H04B2001/0408
Abstract: A method and apparatus for attenuating transmit digital to analog converter (DAC) spurs is provided. The method begins when a reference voltage is injected into an amplifier. Next, an output of the ground low drop-out regulator is measured and is them compared with the reference voltage. The output of the amplifier is then adjusted based on the results of the comparison. If the reference voltage is higher then the output of the ground low drop-out regulator the output of the amplifier is adjusted to ground. If the reference voltage is lower than the output of the ground low drop-out regulator then the output of the amplifier is adjusted to match the reference voltage.
Abstract translation: 提供了用于衰减发射数模转换器（DAC）杂散的方法和装置。 当将参考电压注入放大器时，该方法开始。 接下来，测量接地低压降稳压器的输出，并将其与参考电压进行比较。 然后根据比较结果调整放大器的输出。 如果参考电压较高，则接地低压降稳压器的输出将放大器的输出调整到地。 如果参考电压低于接地低压降稳压器的输出，则调节放大器的输出以匹配参考电压。
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Patent Agency Ranking
4.发明申请TECHNIQUES TO REDUCE HARMONIC DISTORTIONS OF IMPEDANCE ATTENUATORS FOR LOW-POWER WIDEBAND HIGH-RESOLUTION DACS 有权减少低功耗宽带高分辨率DAC的阻抗衰减器谐波失真的技术公开(公告)号：US20140266830A1
公开(公告)日：2014-09-18
申请号：US13839763
申请日：2013-03-15
Applicant: QUALCOMM INCORPORATED
Inventor： Tongyu Song , Sang Min Lee , Derui Kong , Dongwon Seo
IPC: H03M1/74
CPC classification number: H03M1/74 , H03F3/19 , H03F3/211 , H03F3/245 , H03F3/45192 , H03F3/4565 , H03F3/72 , H03F2203/45466 , H03F2203/45512 , H03F2203/45562 , H03F2203/45631 , H03F2203/45634 , H03F2203/45644 , H03F2203/45686 , H03F2203/45701 , H03F2203/45702 , H03F2203/7236 , H03M1/0614
Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.
Abstract translation: 数模转换器（DAC）部分地包括响应于数字信号向一对当前求和节点提供电流的多个输入级，以及耦合在当前求和节点和输出端之间的阻抗衰减器 的DAC。 除了其他功能之外，阻抗衰减器还适用于增加输出负载的阻抗范围，以解决由于工艺，电压和温度的变化而导致的输出负载阻抗的变化，并且将由求和所看到的阻抗解耦 节点从负载阻抗。 阻抗衰减器还包括具有可编程共模增益带宽的差分输入差分输出放大器，以控制放大器的谐波失真。 阻抗衰减器可选地包括一对交叉耦合电容器，以控制放大器的谐波失真。
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5.发明授权Techniques to reduce harmonic distortions of impedance attenuators for low-power wideband high-resolution DACs 有权降低低功耗宽带高分辨率DAC阻抗衰减器谐波失真的技术公开(公告)号：US08872685B2
公开(公告)日：2014-10-28
申请号：US13839763
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Tongyu Song , Sang Min Lee , Derui Kong , Dongwon Seo
CPC classification number: H03M1/74 , H03F3/19 , H03F3/211 , H03F3/245 , H03F3/45192 , H03F3/4565 , H03F3/72 , H03F2203/45466 , H03F2203/45512 , H03F2203/45562 , H03F2203/45631 , H03F2203/45634 , H03F2203/45644 , H03F2203/45686 , H03F2203/45701 , H03F2203/45702 , H03F2203/7236 , H03M1/0614
Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.
Abstract translation: 数模转换器（DAC）部分地包括响应于数字信号向一对当前求和节点提供电流的多个输入级，以及耦合在当前求和节点和输出端之间的阻抗衰减器 的DAC。 除了其他功能之外，阻抗衰减器还适用于增加输出负载的阻抗范围，以解决由于工艺，电压和温度的变化而导致的输出负载阻抗的变化，并且将由总和看到的阻抗解耦 节点从负载阻抗。 阻抗衰减器还包括具有可编程共模增益带宽的差分输入差分输出放大器，以控制放大器的谐波失真。 阻抗衰减器可选地包括一对交叉耦合电容器，以控制放大器的谐波失真。
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公开(公告)号：US10985737B2
公开(公告)日：2021-04-20
申请号：US16516114
申请日：2019-07-18
Applicant: QUALCOMM Incorporated
Inventor： Tongyu Song
IPC: H03K19/0175 , H03K3/012 , H03K3/037 , H04W56/00 , H04W52/02 , H04L7/033 , H03K19/0185 , H03L7/08
Abstract: A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.
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公开(公告)号：US10663993B2
公开(公告)日：2020-05-26
申请号：US15269881
申请日：2016-09-19
Applicant: QUALCOMM Incorporated
Inventor： Tongyu Song , Jeffrey Mark Hinrichs
Abstract: A voltage regulator includes a band limited reference voltage. The band limited reference voltage is generated from a supply voltage combined with a feedback path to provide a band reject power supply rejection ratio (PSRR). The voltage regulator also includes a feedforward path to extend the band reject PSRR.
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公开(公告)号：US08847801B2
公开(公告)日：2014-09-30
申请号：US13779122
申请日：2013-02-27
Applicant: QUALCOMM Incorporated
Inventor： Tongyu Song
IPC: H03M1/10
CPC classification number: H03M1/1009 , H03M1/1061 , H03M1/742
Abstract: Circuits, methods, non-transitory storage media can be configured to reduce calibration errors in a signal converter. A digital-to-analog converter can include a calibration circuit configured to calibrate a digital-to-analog converter (DAC) bit element using a residual error from a previously calibrated digital-to-analog converter (DAC) bit element. The residual error can be stored in memory.
Abstract translation: 电路，方法，非暂时性存储介质可以配置为减少信号转换器中的校准误差。 数模转换器可以包括被配置为使用来自先前校准的数模转换器（DAC）位元素的残差来校准数模转换器（DAC）位元件的校准电路。 剩余错误可以存储在内存中。
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