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1.发明申请公开(公告)号：US20200089645A1
公开(公告)日：2020-03-19
申请号：US16569816
申请日：2019-09-13
Applicant: QUALCOMM Incorporated
Inventor： Yiftach Benjamini , Lior Amarilio , Amit Gil , James Lionel Panian , Dafna Shaool
Abstract: Security techniques for a Peripheral Component Interconnect (PCI) express (PCIE) system include a transport layer protocol (TLP) packet that has a prepended TLP prefix indicating the security features of the TLP packet and an integrity check value (ICV) appended to the TLP packet. The ICV is based on the TLP packet and any TLP prefixes including a security prefix. At a receiver, if the ICV does not match, then the receiver has evidence that the TLP packet may have been subjected to tampering. Further, the TLP packet may be encrypted to prevent snooping, and this feature would be indicated in the TLP prefix. Still further, the TLP prefix may include a counter that may be used to prevent replay attacks. PCIE contemplates flexible TLP prefixes, and thus, the standard readily accommodates the addition of a TLP prefix which indicates the security features of the TLP packet.
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2.发明授权Configurable host interface using multi-radio device and architecture for WLAN offload 有权可配置的主机接口使用多无线电设备和架构进行WLAN卸载公开(公告)号：US09420613B2
公开(公告)日：2016-08-16
申请号：US13830336
申请日：2013-03-14
Applicant: Qualcomm Incorporated
Inventor： James Lionel Panian , Richard Dominic Wietfeldt , Steven F Harris , Gerardo Giaretta , Uppinder Singh Babbar , Sivaramakrishna Veerepalli , Marcello Vincenzo Lioy , Ajith Tom Payyappilly , Andrew M Davidson , Arnaud Meylan , Ramaswamy Venkateshwaran
Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. A multi-radio device controls wireless communications by identifying one or more connection points between radio(s) of the multi-radio device and an operating system executing on a host device, analyzing a policy relating to the multi-radio device, and exposing, to the operating system, a subset of the connection points based on the policy. A modem manages a connection to an applications processor (AP) by virtualizing physical communication interfaces at the modem, providing a single Internet protocol (IP) interface representing the virtualized physical communication interfaces to a high level operating system (HLOS) at the AP, detecting a physical communication interface connected to the modem, and determining whether to expose the detected physical communication interface to the HLOS as a standalone virtualized physical communication interface, or hide the detected physical communication interface as part of an existing virtualized physical communication interface.
Abstract translation: 提供了一种用于无线通信的方法，装置和计算机程序产品。 多无线电设备通过识别多无线电设备的无线电设备和在主机设备上执行的操作系统之间的一个或多个连接点来控制无线通信，分析与多无线电设备相关的策略， 根据策略向操作系统提供连接点的子集。 调制解调器通过虚拟化调制解调器上的物理通信接口来管理与应用处理器（AP）的连接，提供表示到AP处的高级操作系统（HLOS）的虚拟物理通信接口的单个因特网协议（IP）接口，检测 连接到调制解调器的物理通信接口，以及确定是否将检测到的物理通信接口公开到HLOS作为独立的虚拟物理通信接口，或者将检测到的物理通信接口隐藏为现有的虚拟物理通信接口的一部分。
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公开(公告)号：US20150301979A1
公开(公告)日：2015-10-22
申请号：US14533431
申请日：2014-11-05
Applicant: QUALCOMM Incorporated
CPC classification number: G06F13/4252 , G06F9/4498 , G06F9/546 , G06F13/4022 , G06F13/4068 , G06F15/76 , G06F2015/761
Abstract: A finite state machine is provided that both serializes virtual GPIO signals and messaging signals and that deserializer virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.
Abstract translation: 提供了一种有限状态机，可将虚拟GPIO信号和消息传送信号串行化，并且解串器虚拟GPIO信号和消息传递信号。 有限状态机将串行化的虚拟GPIO信号和消息传递信号帧分成由起始位和结束位分隔的帧。
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4.发明申请CONFIGURABLE HOST INTERFACE USING MULTI-RADIO DEVICE AND ARCHITECTURE FOR WLAN OFFLOAD 有权使用多无线设备和无线局域网卸载架构的可配置主机接口公开(公告)号：US20140010221A1
公开(公告)日：2014-01-09
申请号：US13830336
申请日：2013-03-14
Applicant: Qualcomm Incorporated
Inventor： James Lionel Panian , Richard Dominic Wietfeldt , Steven F. Harris , Gerardo Giaretta , Uppinder Singh Babbar , Sivaramakrishna Veerepalli , Marcello Vincenzo Lioy , Ajith Tom Payyappilly , Andrew M. Davidson , Arnaud Meylan , Ramaswamy Venkateshwaran
IPC: H04W76/02
Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. A multi-radio device controls wireless communications by identifying one or more connection points between radio(s) of the multi-radio device and an operating system executing on a host device, analyzing a policy relating to the multi-radio device, and exposing, to the operating system, a subset of the connection points based on the policy. A modem manages a connection to an applications processor (AP) by virtualizing physical communication interfaces at the modem, providing a single Internet protocol (IP) interface representing the virtualized physical communication interfaces to a high level operating system (HLOS) at the AP, detecting a physical communication interface connected to the modem, and determining whether to expose the detected physical communication interface to the HLOS as a standalone virtualized physical communication interface, or hide the detected physical communication interface as part of an existing virtualized physical communication interface.
Abstract translation: 提供了一种用于无线通信的方法，装置和计算机程序产品。 多无线电设备通过识别多无线电设备的无线电设备和在主机设备上执行的操作系统之间的一个或多个连接点来控制无线通信，分析与多无线电设备相关的策略， 根据策略向操作系统提供连接点的子集。 调制解调器通过虚拟化调制解调器上的物理通信接口来管理与应用处理器（AP）的连接，提供表示到AP处的高级操作系统（HLOS）的虚拟物理通信接口的单个因特网协议（IP）接口，检测 连接到调制解调器的物理通信接口，以及确定是否将检测到的物理通信接口公开到HLOS作为独立的虚拟物理通信接口，或者将检测到的物理通信接口隐藏为现有虚拟物理通信接口的一部分。
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公开(公告)号：US20250086136A1
公开(公告)日：2025-03-13
申请号：US18466299
申请日：2023-09-13
Applicant: QUALCOMM Incorporated
Inventor： Ravindranath DODDI , Umamaheshwaran V , Afreen HAIDER , Lekhya Pavani GODAVARTHI , Harinatha Reddy RAMIREDDY , James Lionel Panian , Ramacharan Sundararaman , Santhosh Reddy Akavaram
Abstract: Various embodiments include methods and devices for implementing Universal Chiplet Interconnect Express (UCIe) link configuration for multi-module chiplets of a computing device. Embodiments may include transitioning a UCIe link in an active state having a first sideband that is active to the UCIe link in a reset state, and initializing at least one sideband for the UCIe link that is a different functional sideband of a multi-module chiplet than the first sideband following the reset state of the UCIe link. Embodiments may include reading sideband data configured to represent a functional sideband of the multi-module chiplet, and initializing the functional sideband as the at least one sideband. Embodiments may include reading sideband data configured to represent at least two functional sidebands of the multi-module chiplet, and initializing at least one functional sideband of the at least two functional sidebands as the at least one sideband.
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Patent Agency Ranking
公开(公告)号：US10241953B2
公开(公告)日：2019-03-26
申请号：US15228877
申请日：2016-08-04
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee Mishra , Richard Dominic Wietfeldt , James Lionel Panian
Abstract: A hybrid virtual general purpose input/output (VGI) architecture is provided including a pair of devices coupled through a high-speed cable. The architecture enables a device to communicate sideband signals through the high-speed cable using two pins coupled to respective interconnects of a bus. In an aspect, the architecture may implement link selection without protocol consolidation where the device may configure the two pins for I2C (or I3C) signaling or VGI signaling. In another aspect, the architecture may implement link bridging with protocol consolidation where the device may transmit (or receive) I2C (or I3C) signals through the high-speed cable using a VGI communication protocol.
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公开(公告)号：US10089275B2
公开(公告)日：2018-10-02
申请号：US15168574
申请日：2016-05-31
Applicant: QUALCOMM Incorporated
Inventor： Ofer Rosenberg , Amit Gil , James Lionel Panian , Piyush Patel , Shaul Yohai Yifrach
Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.
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公开(公告)号：US20170039162A1
公开(公告)日：2017-02-09
申请号：US15228877
申请日：2016-08-04
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee Mishra , Richard Dominic Wietfeldt , James Lionel Panian
IPC: G06F13/42
CPC classification number: G06F13/4282 , G06F13/385
Abstract: A hybrid virtual general purpose input/output (VGI) architecture is provided including a pair of devices coupled through a high-speed cable. The architecture enables a device to communicate sideband signals through the high-speed cable using two pins coupled to respective interconnects of a bus. In an aspect, the architecture may implement link selection without protocol consolidation where the device may configure the two pins for I2C (or I3C) signaling or VGI signaling. In another aspect, the architecture may implement link bridging with protocol consolidation where the device may transmit (or receive) I2C (or I3C) signals through the high-speed cable using a VGI communication protocol.
Abstract translation: 提供了混合虚拟通用输入/输出（VGI）架构，包括通过高速电缆耦合的一对设备。 该架构使得设备能够使用耦合到总线的相应互连的两个引脚通过高速电缆来传送边带信号。 在一方面，架构可以实现链路选择而不进行协议整合，其中设备可以配置用于I2C（或I3C）信令或VGI信令的两个引脚。 另一方面，架构可以实现与协议合并的链路桥接，其中设备可以使用VGI通信协议通过高速电缆传输（或接收）I2C（或I3C）信号。
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公开(公告)号：US20160371208A1
公开(公告)日：2016-12-22
申请号：US15184124
申请日：2016-06-16
Applicant: QUALCOMM Incorporated
Inventor： Ofer Rosenberg , Amit Gil , James Lionel Panian , Piyush Patel , Shaul Yohai Yifrach
Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.
Abstract translation: 公开了扩展消息信号中断（MSI）数据。 在一个方面，MSI比特被修改为包括系统级标识符。 在示例性方面，MSI消息数据的高16位被修改为系统级标识符。 通过在MSI消息数据内提供系统级标识符，中断控制器可以验证中断源。
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公开(公告)号：US12079055B2
公开(公告)日：2024-09-03
申请号：US17949968
申请日：2022-09-21
Applicant: QUALCOMM Incorporated
Inventor： James Lionel Panian , John Eaton , Lakshmi Baskaran , Shrinivas Gopalan Uppili
IPC: G06F1/28 , G06F13/42 , H03K19/0185
CPC classification number: G06F1/28 , G06F13/4221 , H03K19/018507 , G06F2213/0026
Abstract: Aspects relate to techniques for controlling signal voltage levels across a wired data link for data communication between apparatuses. A first device can advertise multiple supported signal voltage levels to a peer device connected by the wired data link. The devices can implement the same signal voltage level(s) or different signal voltage levels. The peer devices can compare and select a compatible signal voltage level for data communication. The first device can provide a signal voltage indication signal that is configurable to a plurality of voltage levels corresponding to a plurality of signal voltages. At least one of the plurality of voltage levels can indicate that the first device can operate the data link at a plurality of signal voltages. In some examples, the wired data link can be a peripheral component interconnect express (PCIe) link.
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