公开(公告)号：US20240413137A1

公开(公告)日：2024-12-12

申请号：US18330435

申请日：2023-06-07

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Joan Rey Villarba Buot ,  Bohan Yan ,  Manuel Aldrete

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

Abstract: Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (“die”) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

公开(公告)号：US20240250009A1

公开(公告)日：2024-07-25

申请号：US18158225

申请日：2023-01-23

Applicant: QUALCOMM Incorporated

Inventor： Seongryul Choi ,  Joan Rey Villarba Buot ,  Kuiwon Kang ,  Zhijie Wang

IPC: H01L23/498 ,  H01L21/288 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/288 ,  H01L21/76829 ,  H01L23/49816 ,  H01L24/04 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/08112 ,  H01L2224/08225 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48225

Abstract: Embedded trace substrates (ETS) having an ETS metallization layer with T-shaped interconnects with reduced-width embedded metal traces, and related integrated circuit (IC) packages and fabrication methods. The ETS includes an outer ETS metallization layer that includes T-shaped interconnects for supporting input/output (I/O) connections between the ETS and another opposing package substrate. To increase density of I/O interconnections, the pitch of the embedded metal traces in the ETS metallization layer is reduced. The T-shaped interconnects also each include an additional metal contact pad that is coupled to a respective embedded metal trace to increase the height of the embedded metal trace to eliminate a vertical connection gap between the ETS and an opposing package substrate. In the T-shape interconnects, their embedded metal traces are reduced in width in a horizontal direction(s) as compared to their respective metal contact pads to provide room for additional metal traces for additional signal routing capacity.

公开(公告)号：US11764076B2

公开(公告)日：2023-09-19

申请号：US17107512

申请日：2020-11-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Joan Rey Villarba Buot ,  Terence Cheung

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L21/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

公开(公告)号：US11637057B2

公开(公告)日：2023-04-25

申请号：US16724247

申请日：2019-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Aniket Patil ,  Jaehyun Yeon

IPC: H01L23/498 ,  H01L21/48

Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

公开(公告)号：US20230114404A1

公开(公告)日：2023-04-13

申请号：US17822589

申请日：2022-08-26

Applicant: QUALCOMM Incorporated

Inventor： Seongryul Choi ,  Kuiwon Kang ,  Joan Rey Villarba Buot

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: Embedded trace substrate (ETS) with embedded metal traces having multiple thicknesses for integrated circuit (IC) package height control, and related IC packages and fabrication methods. The IC package includes a die that is coupled to a package substrate to provide signal routing paths to the die. The IC package also includes an ETS that includes metal traces embedded in an insulating layer(s) to provide connections for signal routing paths for the IC package. To control (such as to reduce) the height of the IC package, the embedded metal traces embedded in an insulating layer in the ETS are provided to have multiple thicknesses (i.e., heights) in a vertical direction. The embedded metal traces in the ETS whose thicknesses affect the overall height of the IC package by being coupled to interconnects external to the ETS in the vertical direction, can be reduced in thickness to control IC package height.

公开(公告)号：US10679919B2

公开(公告)日：2020-06-09

申请号：US16016888

申请日：2018-06-25

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Zhijie Wang ,  Bohan Yan

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.

公开(公告)号：US20230215849A1

公开(公告)日：2023-07-06

申请号：US17647141

申请日：2022-01-05

Applicant: QUALCOMM Incorporated

Inventor： Seongryul Choi ,  Kuiwon Kang ,  Michelle Yejin Kim

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L21/4853 ,  H01L24/16 ,  H01L23/58 ,  H01L23/49827 ,  H01L23/49822 ,  H01L21/4857 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/19102 ,  H01L2924/19041

Abstract: Integrated circuit (IC) packages employing a package substrate with embedded deep trench capacitor(s) (DTC(s)) face-up to a semiconductor die (“die”) for connection, and related fabrication methods. A DTC is embedded in a cavity in the package substrate and coupled to a die. To minimize connection path length between the DTC and the die to reduce impedance and improve capacitor performance, the DTC is disposed in a cavity in the package substrate face-up towards the die. The DTC interconnects of the DTC are oriented face-up towards the die in a vertical direction. Also, to minimize connection path length between the DTC and the die, the DTC can be disposed in the package substrate underneath the die in the vertical direction. The DTC interconnects can be disposed in a die-side metallization layer of the package substrate and coupled to external, die-side interconnects of the package substrate.

公开(公告)号：US11552023B2

公开(公告)日：2023-01-10

申请号：US16913288

申请日：2020-06-26

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Brigham Navaja ,  Marcus Hsu ,  Terence Cheung

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/522 ,  H01L21/768 ,  H01L21/48 ,  H01L49/02

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

公开(公告)号：US11545435B2

公开(公告)日：2023-01-03

申请号：US16946104

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Zhijie Wang ,  Hong Bok We

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

Abstract: Some features pertain to a substrate that includes a first portion of the substrate including a first plurality of metal layers, a second portion of the substrate including a second plurality of metal layers, and a plurality of insulating layers configured to separate the first plurality of metal layers and the second plurality of metal layers. A first plurality of posts and a plurality of interconnects are coupled together such that the first plurality of posts and the plurality of interconnects couple the first portion of the substrate to the second portion of the substrate.

公开(公告)号：US11444019B2

公开(公告)日：2022-09-13

申请号：US16840752

申请日：2020-04-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Kuiwon Kang

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) at least one inner dielectric layer, (ii) a plurality of interconnects located in the at least one inner dielectric layer, where the plurality of interconnects includes a pad located on a bottom metal layer of the substrate, (iii) an outer dielectric layer located over the at least one dielectric layer, (iv) at least one routing interconnect coupled to the plurality of interconnects, where the at least one routing interconnect is located over the outer dielectric layer, where the at least one routing interconnect is located below the bottom metal layer of the substrate, and (v) a cover dielectric layer located over the outer dielectric layer and the at least one routing interconnect. The package includes a solder interconnect coupled to the pad located on the bottom metal layer of the substrate.