CAPACITOR WITH LOW EQUIVALENT SERIES INDUCTANCE
    1.
    发明申请
    CAPACITOR WITH LOW EQUIVALENT SERIES INDUCTANCE 审中-公开
    具有低等效系列电感的电容器

    公开(公告)号:US20150255216A1

    公开(公告)日:2015-09-10

    申请号:US14201469

    申请日:2014-03-07

    Abstract: A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding.

    Abstract translation: 具有低等效串联电感的电容器包括与连接在一起的交替的电极层并联布置的多个电极层,以形成电容器的两个电极。 第一组电极层通过外壁连接。 第二组电极层通过中心柱连接。 电容器上的端子可以在表面上间隔开,使得当电容器安装在印刷电路板或集成电路封装上时可以方便地布线信号。 端子可以包括在电容器的相对表面上以提供堆叠。 此外,其中一个端子基本上围绕另一个端子并且可以提供电磁屏蔽。

    HYBRID PARALLEL REGULATOR AND POWER SUPPLY COMBINATION FOR IMPROVED EFFICIENCY AND DROOP RESPONSE WITH DIRECT CURRENT DRIVEN OUTPUT STAGE ATTACHED DIRECTLY TO THE LOAD
    2.
    发明申请
    HYBRID PARALLEL REGULATOR AND POWER SUPPLY COMBINATION FOR IMPROVED EFFICIENCY AND DROOP RESPONSE WITH DIRECT CURRENT DRIVEN OUTPUT STAGE ATTACHED DIRECTLY TO THE LOAD 有权
    混合并联稳压器和电源组合,用于直接连接到负载的直接电流驱动输出级的改进效率和响应

    公开(公告)号:US20160179181A1

    公开(公告)日:2016-06-23

    申请号:US14579899

    申请日:2014-12-22

    Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

    Abstract translation: 诸如移动电话等复杂设备的片上系统芯片(SoC)集成电路的运行模式变化会导致电流需求的尖峰,从而导致电压下降,从而破坏了SoC的运行。 混合并联电源并联连接开关电源和低压差稳压器,以提供高效率和快速的响应时间。 电压调节器在SoC上的集成可减少电压调节器和负载之间的寄生阻抗,有助于降低电压下降。 开关电源和低压差稳压器可以将其输出调节为稍微不同的电压电平。 这可以允许开关电源供应大部分SoC的当前需求。

    CAPACITIVELY-COUPLED HYBRID PARALLEL POWER SUPPLY
    3.
    发明申请
    CAPACITIVELY-COUPLED HYBRID PARALLEL POWER SUPPLY 有权
    电容耦合混合并联电源

    公开(公告)号:US20160216723A1

    公开(公告)日:2016-07-28

    申请号:US14606753

    申请日:2015-01-27

    Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

    Abstract translation: 诸如移动电话等复杂设备的片上系统芯片(SoC)集成电路的运行模式变化会导致电流需求的尖峰,从而导致电压下降,从而破坏了SoC的运行。 混合并联电源并联电容耦合开关电源和低压差稳压器,以提供高效率和快速的响应时间。 低压差稳压器可以包括驱动耦合电容器的AB类运算跨导放大器。 开关电源和低压差稳压器可以将其输出调节为稍微不同的电压电平。 这可以允许开关电源供应大部分SoC的当前需求。

    MULTILAYER CERAMIC CAPACITOR
    6.
    发明申请
    MULTILAYER CERAMIC CAPACITOR 审中-公开
    多层陶瓷电容器

    公开(公告)号:US20150310990A1

    公开(公告)日:2015-10-29

    申请号:US14261373

    申请日:2014-04-24

    CPC classification number: H01G4/30 H01G4/012 H01G4/12 H01G4/232

    Abstract: Aspects of a method of manufacturing a capacitor are provided. The method includes layering a plurality of dielectric plates. The plurality of dielectric plates includes a first dielectric plate having a first conductive region and a second conductive region on a surface of the first dielectric plate. The method further includes forming an inner electrode through an axis of the layered plurality of dielectric plates. The inner electrode electrically couples to the first conductive region on the surface of the first dielectric plate. The method further includes forming an outer electrode, where the outer electrode electrically couples to the second conductive region on the surface of the first dielectric plate.

    Abstract translation: 提供制造电容器的方法的方面。 该方法包括层叠多个电介质板。 多个电介质板包括在第一电介质板的表面上具有第一导电区域和第二导电区域的第一电介质板。 该方法还包括通过层叠的多个电介质板的轴线形成内部电极。 内部电极电耦合到第一电介质板的表面上的第一导电区域。 该方法还包括形成外部电极,其中外部电极电耦合到第一电介质板的表面上的第二导电区域。

Patent Agency Ranking