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1.发明授权公开(公告)号：US11626359B2
公开(公告)日：2023-04-11
申请号：US17242083
申请日：2021-04-27
Applicant: QUALCOMM Incorporated
Inventor： Biancun Xie , Shree Krishna Pandey , Irfan Khan , Miguel Miranda Corbalan , Stanley Seungchul Song
IPC: H01L23/498 , H01L21/48 , H01L25/065
Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.
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公开(公告)号：US20150255216A1
公开(公告)日：2015-09-10
申请号：US14201469
申请日：2014-03-07
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee Mishra , Shree Krishna Pandey , Irfan Khan , Nazanin Darbanian , John David Eaton
CPC classification number: H01G4/30 , H01G2/06 , H01G4/242 , H01G4/35 , H05K1/0231 , H05K1/182 , H05K2201/09345 , H05K2201/10015 , H05K2201/10515 , H05K2201/1053 , H05K2201/10636 , H05K2201/10643 , Y02P70/611
Abstract: A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding.
Abstract translation: 具有低等效串联电感的电容器包括与连接在一起的交替的电极层并联布置的多个电极层，以形成电容器的两个电极。 第一组电极层通过外壁连接。 第二组电极层通过中心柱连接。 电容器上的端子可以在表面上间隔开，使得当电容器安装在印刷电路板或集成电路封装上时可以方便地布线信号。 端子可以包括在电容器的相对表面上以提供堆叠。 此外，其中一个端子基本上围绕另一个端子并且可以提供电磁屏蔽。
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公开(公告)号：US11749661B2
公开(公告)日：2023-09-05
申请号：US17364318
申请日：2021-06-30
Applicant: QUALCOMM Incorporated
Inventor： Biancun Xie , Shree Krishna Pandey
CPC classification number: H01L25/18 , H01L25/50 , H01L27/013 , H01L28/40
Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.
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公开(公告)号：US20160216723A1
公开(公告)日：2016-07-28
申请号：US14606753
申请日：2015-01-27
Applicant: QUALCOMM Incorporated
Inventor： Zhengming Fu , James Thomas Doyle , Nazanin Darbanian , Shree Krishna Pandey , Yi Cao
IPC: G05F3/08
CPC classification number: G05F3/08 , G05F1/575 , H02M3/158 , H02M3/1582 , H02M2001/0045 , H02M2003/1566
Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
Abstract translation: 诸如移动电话等复杂设备的片上系统芯片（SoC）集成电路的运行模式变化会导致电流需求的尖峰，从而导致电压下降，从而破坏了SoC的运行。 混合并联电源并联电容耦合开关电源和低压差稳压器，以提供高效率和快速的响应时间。 低压差稳压器可以包括驱动耦合电容器的AB类运算跨导放大器。 开关电源和低压差稳压器可以将其输出调节为稍微不同的电压电平。 这可以允许开关电源供应大部分SoC的当前需求。
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公开(公告)号：US09319218B2
公开(公告)日：2016-04-19
申请号：US14315142
申请日：2014-06-25
Applicant: QUALCOMM Incorporated
Inventor： Shree Krishna Pandey , Arun Chandra Kundu , George Alan Wiley , Chulkyu Lee
CPC classification number: H04L7/0041 , H04B3/00 , H04B3/462 , H04B3/542 , H04L25/0264
Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.
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Patent Agency Ranking
公开(公告)号：US20240107665A1
公开(公告)日：2024-03-28
申请号：US17934651
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Biancun Xie , Shree Krishna Pandey , Chin-Kwan Kim , Ryan Lane , Charles David Paynter
CPC classification number: H05K1/0298 , H05K3/4644 , H05K2201/093 , H05K2201/09309 , H05K2201/10015 , H05K2201/10734
Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.
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7.发明授权Metal-insulator-metal (MIM) capacitor in redistribution layer (RDL) of an integrated device 有权集成器件再分配层（RDL）中的金属绝缘体金属（MIM）电容器公开(公告)号：US09577025B2
公开(公告)日：2017-02-21
申请号：US14181522
申请日：2014-02-14
Applicant: QUALCOMM Incorporated
Inventor： Shiqun Gu , Ryan David Lane , Glenn David Raskin , Shree Krishna Pandey
IPC: H01L49/02 , H01L23/00 , H01L23/538 , H01L23/522
CPC classification number: H01L28/60 , H01L23/5223 , H01L23/5383 , H01L23/5389 , H01L24/02 , H01L24/19 , H01L24/96 , H01L2224/0231 , H01L2224/02331 , H01L2224/02371 , H01L2224/02373 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05572 , H01L2224/12105 , H01L2224/24137 , H01L2924/1205
Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor.
Abstract translation: 一些特征涉及包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层和耦合到金属层之一的再分配部分的集成器件。 再分配部分包括第一金属再分布层，耦合到第一金属再分布层的绝缘层和耦合到绝缘层的第二金属再分配层。 第一金属再分布层，绝缘层和第二金属再分配层被配置为在集成器件中作为电容器工作。 在一些实施方案中，电容器是金属 - 绝缘体 - 金属（MIM）电容器。
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公开(公告)号：US20140252637A1
公开(公告)日：2014-09-11
申请号：US13926830
申请日：2013-06-25
Applicant: QUALCOMM Incorporated
Inventor： Shree Krishna Pandey , Changyu Sun
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5036 , G06F17/5077 , G06F2217/82
Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.
Abstract translation: 提供了一种用于无线通信的方法，装置和计算机程序产品。 该装置为由水平互连占据的一组纵向通道产生多个互连图案。 每个互连图案可以不同于其他互连图案。 每个互连图案可以限定该组水平互连和间隙通道的相对位置。 对于每个互连图案确定最高串扰，并且选择具有最小最高串扰的互连图案作为优选图案。 最高串扰可能包括远端串扰或近端串扰，并且可以针对频率范围或多个频率来计算。 可以通过将互连模型化为传输线来计算串扰。
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公开(公告)号：US12160952B2
公开(公告)日：2024-12-03
申请号：US17934651
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Biancun Xie , Shree Krishna Pandey , Chin-Kwan Kim , Ryan Lane , Charles David Paynter
Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.
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公开(公告)号：US09891646B2
公开(公告)日：2018-02-13
申请号：US14606753
申请日：2015-01-27
Applicant: QUALCOMM Incorporated
Inventor： Zhengming Fu , James Thomas Doyle , Nazanin Darbanian , Shree Krishna Pandey , Yi Cao
CPC classification number: G05F3/08 , G05F1/575 , H02M3/158 , H02M3/1582 , H02M2001/0045 , H02M2003/1566
Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
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