CIRCUITS AND METHODS PROVIDING SUPPLY VOLTAGE CONTROL BASED ON TRANSIENT LOAD PREDICTION
    7.
    发明申请
    CIRCUITS AND METHODS PROVIDING SUPPLY VOLTAGE CONTROL BASED ON TRANSIENT LOAD PREDICTION 有权
    基于瞬态负载预测提供电源电压控制的电路和方法

    公开(公告)号:US20160132084A1

    公开(公告)日:2016-05-12

    申请号:US14938655

    申请日:2015-11-11

    Abstract: An apparatus and method are disclosed for providing voltage control at a load of a buck converter. The buck converter is in a feedback loop so that a reference voltage determines a pulse width modulated (PWM) signal that is fed to the buck converter, and an output voltage of the buck converter is fed back to a PWM control circuit to maintain a value of the output voltage. The load at the buck converter provides event counters to a transient load current prediction circuit, which uses a curve fitting algorithm or other adaptive control algorithm to predict a change in current at the load. The transient load current prediction circuit then manipulates the reference voltage in accordance with the predicted change in current at the load.

    Abstract translation: 公开了一种用于在降压转换器的负载处提供电压控制的装置和方法。 降压转换器处于反馈回路中,使得参考电压确定馈送到降压转换器的脉宽调制(PWM)信号,并且降压转换器的输出电压被反馈到PWM控制电路以维持值 的输出电压。 降压转换器的负载为瞬态负载电流预测电路提供事件计数器,该电路使用曲线拟合算法或其他自适应控制算法来预测负载电流的变化。 然后,瞬态负载电流预测电路根据预测的负载电流变化来操纵参考电压。

    CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER
    8.
    发明申请
    CIRCUITS AND METHODS PROVIDING DEAD TIME ADJUSTMENT AT A SYNCHRONOUS BUCK CONVERTER 有权
    在同步转换器上提供死区时间调整的电路和方法

    公开(公告)号:US20160118893A1

    公开(公告)日:2016-04-28

    申请号:US14918893

    申请日:2015-10-21

    Abstract: An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.

    Abstract translation: 公开了一种用于在诸如同步降压转换器的电压调节器处有效地使用电力的装置和方法。 同步降压转换器包括分别由第一控制信号和第二控制信号操作的第一开关和第二开关,其中第一和第二控制信号具有相应的相位差。 逻辑电路针对第一控制信号和第二控制信号之间的相位差的迭代变化来测量输入脉宽调制(PWM)信号的占空比。 逻辑电路选择与PWM信号的最小值相对应的相位差,从而优化同步降压转换器的死区时间。 逻辑电路可以包括数字脉宽调制器。

    Substrate-less discrete coupled inductor structure

    公开(公告)号:US10115661B2

    公开(公告)日:2018-10-30

    申请号:US13791388

    申请日:2013-03-08

    Abstract: Some novel features pertain to an inductor structure that includes a first inductor winding, a second inductor winding and a filler. The first inductor winding includes an electrically conductive material. The second inductor winding includes an electrically conductive material. The filler is laterally located between the first inductor winding and the second inductor winding. The filler is configured to provide structural coupling of the first and second inductor windings. In some implementations, the first inductor winding is laterally co-planar to the second inductor winding. In some implementations, the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the filler is an epoxy.

    Circuits and methods for controlling a three-level buck converter

    公开(公告)号:US09793804B2

    公开(公告)日:2017-10-17

    申请号:US14630362

    申请日:2015-02-24

    CPC classification number: H02M3/158 H02M1/126 H02M3/07 H02M7/483 H02M2003/072

    Abstract: A circuit including: a control system for a three-level buck converter, the three-level buck converter including multiple input switches, each of the input switches receiving one of a plurality of different pulse width modulated signals, the control system including: a first clock signal and a second clock signal, the second clock signal being a phase-shifted version of the first clock signal; ramp generating circuitry receiving the first and second clock signals and producing first and second ramp signals, respectively, from the first and second clock signals; a first comparing circuit receiving the first ramp signal and producing a first one of the pulse width modulated signals therefrom; and a second comparing circuit receiving the second ramp signal and producing a second one of the pulse width modulated signals therefrom.

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