公开(公告)号：US09520165B1

公开(公告)日：2016-12-13

申请号：US14745216

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Nishith Nitin Desai ,  Tony Chung Yiu Kwok ,  Changho Jung

IPC: G11C7/12 ,  G11C11/4094 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C11/419 ,  G11C2207/002

Abstract: A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.

Abstract translation: 提供诸如PDP SRAM的伪双端口（PDP）存储器，其独立地控制位线预充电和感测放大器预充电以增加存储器操作速度，同时消除或减少撬棒电流的放电。

公开(公告)号：US10061542B2

公开(公告)日：2018-08-28

申请号：US14855319

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu Kwok ,  Nishith Nitin Desai ,  Changho Jung

IPC: G06F3/06 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22 ,  G06F13/16

CPC classification number: G06F3/0683 ,  G06F3/0611 ,  G06F3/0659 ,  G06F13/1689 ,  G11C7/1075 ,  G11C7/22 ,  G11C11/419

Abstract: Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.

公开(公告)号：US20150310901A1

公开(公告)日：2015-10-29

申请号：US14261192

申请日：2014-04-24

Applicant: QUALCOMM INCORPORATED

Inventor： Changho Jung ,  Rakesh Vattikonda ,  Tony Chung Yiu Kwok

IPC: G11C7/12 ,  G11C5/14

CPC classification number: G11C7/12 ,  G11C5/148 ,  G11C7/18 ,  G11C8/16 ,  G11C11/417

Abstract: A memory and a method for operating the memory having a sleep mode are provided. The memory one or more storage elements and a bitline coupled to the one or more storage elements. A precharge circuit is configured to precharge the bitline during a precharge period and float the bitline during a sleep mode. An operating circuit coupled to the one or more storage elements, wherein at least one of the operating circuit and the one or more storage elements being configured to remain electrically coupled to a supply voltage in the sleep mode.

Abstract translation: 提供了一种用于操作具有休眠模式的存储器的存储器和方法。 存储器一个或多个存储元件和耦合到一个或多个存储元件的位线。 预充电电路被配置为在预充电周期期间预充电位线，并且在睡眠模式期间浮动位线。 耦合到所述一个或多个存储元件的操作电路，其中所述操作电路和所述一个或多个存储元件中的至少一个被配置为在睡眠模式下保持电耦合到电源电压。

公开(公告)号：US09978444B2

公开(公告)日：2018-05-22

申请号：US15077636

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu Kwok ,  Changho Jung

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/227 ,  G11C8/18 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.

公开(公告)号：US09978442B2

公开(公告)日：2018-05-22

申请号：US15258964

申请日：2016-09-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Liang ,  Tony Chung Yiu Kwok ,  Rui Li ,  Sei Seung Yoon

IPC: G11C11/4076 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C11/418 ,  G11C7/1072 ,  G11C7/227 ,  G11C8/18 ,  G11C11/419 ,  G11C13/0061

Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.

公开(公告)号：US09653152B1

公开(公告)日：2017-05-16

申请号：US15352197

申请日：2016-11-15

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu Kwok ,  Changho Jung

IPC: G06F12/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G06F13/1668 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418 ,  G11C2207/2209

Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory controller that includes a logic circuit configured to generate a select signal for selecting between first and second ports of a memory as a function of first and second port signals. Additionally, the memory controller includes a switch configured to connect and disconnect the first and the second port signals. In another aspect of the disclosure, the apparatus is a storage apparatus that includes a memory and a memory controller. The memory controller includes a latch configured to latch a first port selection signal to produce a first port signal and latch a second port selection signal to produce a second port signal. The memory controller also includes a switch configured to connect and disconnect the first and the second port signals and a logic circuit configured to generate a select signal.

公开(公告)号：US20160372167A1

公开(公告)日：2016-12-22

申请号：US14745216

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Nishith Nitin Desai ,  Tony Chung Yiu Kwok ,  Changho Jung

IPC: G11C7/12 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C11/419 ,  G11C2207/002

Abstract: A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.

Abstract translation: 提供诸如PDP SRAM的伪双端口（PDP）存储器，其独立地控制位线预充电和感测放大器预充电以增加存储器操作速度，同时消除或减少撬棒电流的放电。

公开(公告)号：US09324416B2

公开(公告)日：2016-04-26

申请号：US14464627

申请日：2014-08-20

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Tony Chung Yiu Kwok ,  Changho Jung ,  Nishith Nitin Desai

IPC: G11C16/04 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412

Abstract: A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

Abstract translation: 用于操作所提供的存储器的存储器和方法。 在一个方面，存储器可以是PDP存储器。 存储器包括控制电路，该控制电路经配置以响应于访问周期的时钟的边沿而产生第一时钟和第二时钟。 第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。 第一输入电路包括锁存器。 第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。 第二输入电路包括触发器。