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公开(公告)号：US10536143B1
公开(公告)日：2020-01-14
申请号：US16570173
申请日：2019-09-13
发明人： Burt Lee Price , Dhaval Shah
IPC分类号： H03K17/22 , G06F1/24 , G01R19/165
摘要： A system is disclosed. The system includes a first stage configured to receive VIN and VREF, the first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes at a common drain a high-gain node having a voltage VHGN. The system further include a second stage coupled to the high-gain node and configured to generate VOUT based on a difference between VIN and VREF, the second stage comprising a resistor and an inverter transistor pair, wherein the gates of the inverter transistor pair are coupled to the high-gain node of the first stage and the resistor couples the high-gain node of first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of first stage.
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公开(公告)号：US20170344102A1
公开(公告)日：2017-11-30
申请号：US15604038
申请日：2017-05-24
发明人： Yeshwant Nagaraj Kolla , Jeffrey Todd Bridges , Sanjay Patel , Shraddha Sridhar , Burt Lee Price , Gabriel Martel Tarr
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/3287 , H02M1/08 , H02M3/157 , H02M2001/0025
摘要： Adaptive voltage modulation circuits for adjusting supply voltage to reduce supply voltage droops and minimize power consumption are provided. In one aspect, an adaptive voltage modulation circuit detects a supply voltage droop by detecting when a supply voltage falls below a droop threshold voltage, and adjusts a clock signal provided to a load circuit in response to a supply voltage droop. The adaptive voltage modulation circuit keeps a count of the number of clock signal cycles during which the supply voltage is below the droop threshold voltage. The adaptive voltage modulation circuit increases the supply voltage in response to the count exceeding an upper threshold value, and decreases the supply voltage in response to the count being less than a lower threshold value at an end of a defined period. The adaptive voltage modulation circuit can reduce the time a load circuit operates with reduced frequency while minimizing power consumption.
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公开(公告)号：US09712126B2
公开(公告)日：2017-07-18
申请号：US15085122
申请日：2016-03-30
IPC分类号： H03F3/45
CPC分类号： H03F3/45071 , H03F3/45973 , H03F2200/153 , H03F2200/78 , H03F2203/45048
摘要： Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages are disclosed. In one aspect, an automatically calibrating op-amp system is provided that employs an analog calibration signal corresponding to a calibration mode to compensate an output voltage signal of an op-amp corresponding to an amplify mode. An automatic calibration circuit is included that employs a successive approximation register (SAR) controller configured to successively generate digital values based on the output voltage signal of the op-amp in response to a mode signal indicating the calibration mode. The automatic calibration circuit includes a digital-to-analog converter (DAC) configured to convert each successive digital value into the analog calibration signal in response to the mode signal indicating the calibration mode. The analog calibration signal is provided to an auxiliary differential input of the op-amp to compensate for the composite offset voltage in the amplify mode.
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4.发明申请DISTRIBUTED VOLTAGE NETWORK CIRCUITS EMPLOYING VOLTAGE AVERAGING, AND RELATED SYSTEMS AND METHODS 有权使用电压平均分布式电压网络电路及相关系统和方法公开(公告)号：US20160070277A1
公开(公告)日：2016-03-10
申请号：US14482456
申请日：2014-09-10
CPC分类号： G05F1/46 , G01R19/003 , G01R31/3004 , H01L22/30
摘要： Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.
摘要翻译： 公开了使用电压平均的分布式电压网络电路，以及相关的系统和方法。 一方面，由于分布式负载电路的一个区域中的电压可以与第二区域中的电压变化，所以分布式电压网络电路被配置为从多个区域分接电压以计算分布式负载电路中的平均电压。 分布式电压网络电路包括具有源节点的电压分配源组件。 电压通过电阻互连从每个源节点分配到相应的电压负载节点。 电压抽头节点访问每个相应的电压负载节点的电压。 每个电压抽头节点耦合到电压平均电路中对应的电阻元件的输入节点。 每个电阻元件的输出节点耦合到电压平均电路的电压输出节点，产生电压输出节点上的分布式负载电路的平均电压。
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公开(公告)号：US10381993B1
公开(公告)日：2019-08-13
申请号：US16045103
申请日：2018-07-25
CPC分类号： H03F3/45995 , H03F1/02 , H03F3/45977 , H03F2200/375
摘要： Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation. The automatic calibration circuit includes a single controller to generate calibration signals to the instrumentation amplifier to reduce or cancel offset voltage, thereby eliminating the need to provide multiple automatic calibration circuits or an automatic calibration circuit employing multiple controllers.
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6.发明申请公开(公告)号：US20190050009A1
公开(公告)日：2019-02-14
申请号：US15672356
申请日：2017-08-09
发明人： Burt Lee Price , Yeshwant Nagaraj Kolla , Dhaval Rajeshbhai Shah , Jin Liang , Yu Sun , Hans Lee Yeager
CPC分类号： G05F1/565 , G01R19/003 , G01R19/0092 , G01R19/10 , G01R19/28 , H02M2001/0009
摘要： Aspects for sensing total current of distributed load circuits independently of a spatial profile of the total current using distributed voltage averaging are disclosed. In one aspect, a current sense circuit is configured to sense total current of a distributed load circuit independently of where current is distributed. The current sense circuit includes distributed voltage averaging circuits configured to determine average voltages of the distributed load circuit based on voltages sensed at multiple resistive paths corresponding to a distribution network configured to provide voltage to the distributed load circuit. An amplifier includes an output node having an output voltage that is proportional to total current flowing in the distributed load circuit. The current sense circuit allows for sensing total current independent of where the current flows, providing more accurate current sensing compared to sensing current in one area of the distributed load circuit.
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公开(公告)号：US09960596B2
公开(公告)日：2018-05-01
申请号：US14862773
申请日：2015-09-23
IPC分类号： H02J1/00 , H02J1/10 , H03K5/24 , H03K19/003 , H03K19/00
CPC分类号： H02J1/10 , H03K5/2481 , H03K19/0016 , H03K19/00315
摘要： Automatic voltage switching circuits for providing a higher voltage of multiple supply voltages are disclosed. In one aspect, an automatic voltage switching circuit is configured to generate a compare signal indicating which of a first supply voltage and a second supply voltage is a higher voltage. The automatic voltage switching circuit is further configured to generate first and second select signals based on the compare signal, wherein the first and second select signals are in a voltage domain of the higher voltage. Transistors corresponding to the first and second supply voltages control switching the output voltage to the higher voltage in response to the first and second select signals. Biasing the back-gates of the transistors using the output voltage reduces or avoids forward biasing in the body diodes of the transistors, thus reducing the possibility of the output voltage causing interference on a power supply corresponding to a non-activated transistor.
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8.发明申请SWITCHED POWER CONTROL CIRCUITS FOR CONTROLLING THE RATE OF PROVIDING VOLTAGES TO POWERED CIRCUITS, AND RELATED SYSTEMS AND METHODS 有权用于控制向电源电路提供电压的开关电源控制电路及相关系统和方法公开(公告)号：US20170047842A1
公开(公告)日：2017-02-16
申请号：US14826472
申请日：2015-08-14
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , H02M2001/0029 , H03K6/04 , H03K17/163 , H03K19/0016
摘要： Switched power control circuits for controlling the rate of providing voltages to powered circuits are disclosed. In one aspect, a switched power control circuit is provided that is configured to control activation of a headswitch circuit such that the headswitch circuit gradually provides a supply voltage to a powered circuit rather than providing full supply voltage in a substantially instantaneous manner. To gradually ramp up an output voltage, the headswitch circuit is configured to provide the output voltage to the powered circuit in response to a control signal received on a control input. The control signal is generated by a control circuit in response to an enable signal. To prevent the headswitch circuit from providing the full supply voltage to the powered circuit instantaneously, a current sink circuit is configured to control a ramping rate of the output voltage generated by the headswitch circuit.
摘要翻译： 公开了用于控制向供电电路提供电压的速率的开关功率控制电路。 一方面，提供一种开关式电源控制电路，其被配置为控制头开关电路的激活，使得头开关电路逐渐向供电电路提供电源电压，而不是以基本上瞬时的方式提供全部电源电压。 为了逐渐升高输出电压，头开关电路被配置为响应于在控制输入端接收到的控制信号而向供电电路提供输出电压。 响应于使能信号，由控制电路产生控制信号。 为了防止头开关电路立即向供电电路提供全电源电压，电流吸收电路被配置为控制由头开关电路产生的输出电压的斜坡率。
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9.发明申请DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACs), AND RELATED CIRCUITS, SYSTEMS, AND METHODS 有权双字模数转换器（DAC）及相关电路，系统和方法公开(公告)号：US20140347202A1
公开(公告)日：2014-11-27
申请号：US14458377
申请日：2014-08-13
摘要： Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.
摘要翻译： 公开了双串数/模转换器（DAC）及相关电路，系统和方法。 在本文公开的实施例中，双串DAC的初级分压器由至少一个调节电路组成。 调整电路被配置为响应于主开关单元选择所选择的电阻器节点对，在次级分压器电路上保持所选择的电阻器节点对的理想电压。 以这种方式，双串DAC的初级分压器和次级分压器电路之间不需要阻抗隔离。 结果，作为非限制性示例，可以减小用于双串DAC的集成电路（IC）上的面积，DAC的功耗可能降低，和/或双串DAC可以具有增加的性能 不需要安置时间。
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10.发明授权公开(公告)号：US10447292B1
公开(公告)日：2019-10-15
申请号：US16113720
申请日：2018-08-27
发明人： Burt Lee Price
摘要： Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SAR ADC circuit includes a number of SAR controller circuits, each of which includes SAR register circuits. Each SAR register circuit receives and stores a corresponding digital bit that is based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal. Each SAR register circuit also provides a corresponding digital signal based on the digital bit. A DAC circuit receives a reference voltage, and uses the reference voltage and a subset of digital signals generated by SAR controller circuits to generate multiple DAC analog signals. A compare circuit generates the digital bit corresponding to each SAR controller circuit, wherein a number of the digital bits are generated in parallel. Each digital bit collectively forms a digital representation of the analog input signal.
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