公开(公告)号：US08270234B1

公开(公告)日：2012-09-18

申请号：US13113303

申请日：2011-05-23

申请人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

发明人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  H03K3/356052 ,  H03K3/356113

摘要： A level shifter including a level shifter module configured to i) receive an input signal, wherein the input signal varies between a first level and a second level, ii) receive a first voltage supply signal and a second voltage supply signal, and iii) generate a latch control signal based on the input signal and one of the first voltage supply signal and the second voltage supply signal. The level shifter further includes a latch module configured to i) receive the latch control signal, ii) receive the second voltage supply signal and a third voltage supply signal, and iii) generate an output signal based on the latch control signal and one of the second voltage supply signal and the third voltage supply signal.

摘要翻译： 一种电平移位器，包括电平移位器模块，其配置为i）接收输入信号，其中所述输入信号在第一电平和第二电平之间变化，ii）接收第一电压供应信号和第二电压供应信号，以及iii）产生 基于输入信号和第一电压供给信号和第二电压供给信号中的一个的锁存器控制信号。 电平移位器还包括锁存模块，其被配置为i）接收锁存控制信号，ii）接收第二电压供应信号和第三电压供应信号，以及iii）基于锁存控制信号产生输出信号，并且 第二电压供给信号和第三电压供给信号。

公开(公告)号：US07948810B1

公开(公告)日：2011-05-24

申请号：US12250021

申请日：2008-10-13

申请人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

发明人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  H03K3/356052 ,  H03K3/356113

摘要： A level shifter includes a level shifter module that receives a first input signal having high and low states and at least one voltage supply signal, and that generates a latch control signal based on the high and low states of the first input signal. A latch module receives the latch control signal, a data input signal, and the at least one voltage supply signal. The latch module selectively stores data associated with the data input signal based on the latch control signal. The latch module selectively changes the at least one voltage supply signal from a first level to a second level and outputs the data according to the second level based on the latch control signal.

摘要翻译： 电平移位器包括电平移位器模块，其接收具有高和低状态的第一输入信号和至少一个电压供应信号，并且基于第一输入信号的高和低状态产生锁存控制信号。 锁存模块接收锁存控制信号，数据输入信号和至少一个电压供应信号。 锁存模块基于锁存控制信号有选择地存储与数据输入信号相关联的数据。 闩锁模块有选择地将至少一个电压供给信号从第一电平改变到第二电平，并且基于锁存控制信号输出根据第二电平的数据。

公开(公告)号：US07746704B1

公开(公告)日：2010-06-29

申请号：US12209794

申请日：2008-09-12

申请人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

发明人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

IPC分类号： G11C16/04

CPC分类号： G11C11/5621 ,  G11C16/10

摘要： A system includes an input that receives a control signal and a program module that initializes a nonvolatile multilevel memory cell based on the control signal. The program module initializes the nonvolatile multilevel memory cell by programming the nonvolatile multilevel memory cell to one of S states of the nonvolatile multilevel memory cell, where S is an integer greater than 1. The one of the S states is different than a lowest one of the S states.

摘要翻译： 系统包括接收控制信号的输入端和基于控制信号初始化非易失性多电平存储单元的程序模块。 程序模块通过将非易失性多级存储器单元编程为非易失性多级存储器单元的S状态之一来初始化非易失性多级存储器单元，其中S是大于1的整数.S状态中的一个不同于 S州。

公开(公告)号：US07724596B1

公开(公告)日：2010-05-25

申请号：US12209577

申请日：2008-09-12

申请人： Pantas Sutardja ,  Yonghua Song ,  Bo Wang ,  Chih-Hsin Wang ,  Qiang Tang

发明人： Pantas Sutardja ,  Yonghua Song ,  Bo Wang ,  Chih-Hsin Wang ,  Qiang Tang

IPC分类号： G11C7/02 ,  H03F3/45

CPC分类号： G11C16/28 ,  G11C7/062 ,  G11C2207/063

摘要： A sensing amplifier for a memory cell comprises a selection stage that outputs one of a reference current and a memory cell current during a first period and the other of the reference current and the memory cell current during a second period. The first period and the second period are non-overlapping. An input stage generates a first current based on the one of the reference current and the memory cell current during the first period and generates a second current based on the other of the reference current and the memory cell current during the second period. A sensing stage senses a first value based on the first current and stores the first value during the first period, senses a second value based on the second current during the second period and compares the first value to the second value.

摘要翻译： 用于存储单元的感测放大器包括选择级，其在第一时段期间输出参考电流和存储单元电流之一，并且在第二时段期间输出参考电流和存储单元电流中的另一个。 第一期与第二期不重叠。 输入级在第一时段期间基于参考电流和存储单元电流之一产生第一电流，并且在第二周期期间基于参考电流和存储单元电流中的另一个产生第二电流。 感测级基于第一电流感测第一值并且在第一周期期间存储第一值，在第二周期期间基于第二电流感测第二值，并将第一值与第二值进行比较。

公开(公告)号：US08248848B1

公开(公告)日：2012-08-21

申请号：US12240123

申请日：2008-09-29

申请人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

发明人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

IPC分类号： G11C16/04 ,  G11C7/06

CPC分类号： G11C16/3445 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2013/0076

摘要： A memory circuit includes a memory array with multi-level cells that are each capable of storing M bits of data, where M is an integer greater than one. A module reads a state of one of the multi-level cells. The module performs at least one of a first erase operation and a first program operation on the one of the multi-level cells for the M bits of data during a first time period.

摘要翻译： 存储器电路包括具有多级单元的存储器阵列，每个单元能够存储M位数据，其中M是大于1的整数。 模块读取多级单元之一的状态。 该模块在第一时间段期间针对M位数据执行多级单元中的一个上的第一擦除操作和第一编程操作中的至少一个。

公开(公告)号：US08792274B1

公开(公告)日：2014-07-29

申请号：US13590230

申请日：2012-08-21

申请人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

发明人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

IPC分类号： G11C16/04 ,  G11C7/06

CPC分类号： G11C16/3445 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2013/0076

摘要： A system is provided and includes an array of cells, a first module, and a third module. The first module reads a state of a cell in the array to detect first bits stored in the cell. The third module, subsequent to the first module reading the state, performs a first operation on a first bit of the first bits and performs the first operation on a first of multiple signal inputs. The signal inputs indicate second bits of data to be stored in the cell. The third module performs a second operation on a second bit of the first bits and performs the second operation on a second one of the signal inputs. The first module, based on results of the first and second operations, performs a first erase operation or a first program operation on the cell to match the state of the cell to the second bits.

摘要翻译： 提供了一种系统，包括一个单元阵列，一个第一模块和一个第三模块。 第一模块读取阵列中的单元的状态以检测存储在单元中的第一位。 第三模块在第一模块读取状态之后，对第一位的第一位执行第一操作，并且在多个信号输入中的第一个上执行第一操作。 信号输入表示要存储在单元中的数据的第二位。 第三模块对第一位的第二位执行第二操作，并对第二信号输入执行第二操作。 第一模块基于第一和第二操作的结果，对单元执行第一擦除操作或第一程序操作，以将该单元的状态与第二位相匹配。

公开(公告)号：US08116110B1

公开(公告)日：2012-02-14

申请号：US12340911

申请日：2008-12-22

申请人： Pantas Sutardja ,  Chih-Hsin Wang ,  Qiang Tang

发明人： Pantas Sutardja ,  Chih-Hsin Wang ,  Qiang Tang

IPC分类号： G11C5/06

CPC分类号： G11C8/12 ,  G11C5/025 ,  G11C16/0416

摘要： A memory device including nonvolatile memory cells arrayed in a first direction and in a second direction, a plurality of first lines extending in the first direction for coupling memory cells arrayed in the first direction, and a plurality of second lines extending in the second direction for coupling memory cells arrayed in the second direction. The memory device includes a plurality of decoders, including i) first decoders coupled to the first lines and ii) second decoders coupled to the second lines, for accessing any one or more of the memory cells in any order. The memory device includes a plurality of segments. Each segment includes different ones of the nonvolatile memory cells. A first one of the segments is juxtaposed to, in the second direction, a second one of the segments. The second one of the segments mirrors, in the second direction, the first one of the segments.

摘要翻译： 一种存储器件，包括沿第一方向和第二方向排列的非易失性存储单元，沿第一方向延伸的多条第一线，用于耦合沿第一方向排列的存储单元，以及沿第二方向延伸的多条第二线， 耦合沿第二方向排列的存储单元。 存储器件包括多个解码器，包括i）耦合到第一线的第一解码器，以及ii）耦合到第二线的第二解码器，用于以任何顺序访问任何一个或多个存储器单元。 存储器件包括多个段。 每个段包括不同的非易失性存储单元。 该段中的第一个与第二个方向并列，分段中的第二个。 第二个片段在第二个方向上反射第一个片段。

公开(公告)号：US08120088B1

公开(公告)日：2012-02-21

申请号：US12105988

申请日：2008-04-18

申请人： Min She ,  Chih-Hsin Wang

发明人： Min She ,  Chih-Hsin Wang

IPC分类号： H01L29/76

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieved with the bit line junctions typically 20 nanometers or shallower while the doping levels in the junctions are below about 5×1019 atoms/cm3.

摘要翻译： 存储单元和阵列降低了位线电阻。 元件导体设置在位线的顶部以减小位线的电阻，同时保持浅位线结，使得通过20位或更浅的位线结实现200欧姆/平方或更小的薄层电阻，同时 结中的掺杂水平低于约5×1019原子/ cm3。

公开(公告)号：US20070253257A1

公开(公告)日：2007-11-01

申请号：US11380418

申请日：2006-04-26

申请人： Chih-Hsin Wang

发明人： Chih-Hsin Wang

IPC分类号： G11C16/04

CPC分类号： H01L29/7885 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324

摘要： Nonvolatile memory cells and array are provided. The memory cell comprises a body, a source, a drain, and a charge storage region. The body comprises an n-type conductivity and is formed in a well of the n-type conductivity. The source and the drain have p-type conductivity and are formed in the well with a channel of the body defined therebetween. The charge storage region is disposed over and insulated from the channel by a channel insulator. Each cell further comprises a bias setting having a source voltage applied to the source, a well voltage applied to the well, and a drain voltage applied to the drain. A bias configuration for an erase operation of the memory cell is further provided, wherein the source voltage is sufficiently more negative with respect to the well voltage and is sufficiently more positive with respect to the drain voltage to inject hot holes onto the charge storage region. The cells can be arranged in row and column to form memory arrays and memory device.

摘要翻译： 提供了非易失性存储单元和阵列。 存储单元包括主体，源极，漏极和电荷存储区域。 该主体包括n型导电性并形成在n型导电性的阱中。 源极和漏极具有p型导电性，并且在阱中形成有在其间限定的主体的沟道。 电荷存储区域通过沟道绝缘体设置在通道上并与通道绝缘。 每个单元还包括具有施加到源极的源极电压，施加到阱的阱电压和施加到漏极的漏极电压的偏置设置。 还提供了用于存储单元的擦除操作的偏置配置，其中源极电压相对于阱电压足够多地为负，并且相对于漏极电压而言足够地为正向，以将热空穴注入电荷存储区域。 单元格可以以行和列排列以形成存储器阵列和存储器件。

公开(公告)号：US07180125B2

公开(公告)日：2007-02-20

申请号：US10962288

申请日：2004-10-08

申请人： Chih-Hsin Wang

发明人： Chih-Hsin Wang

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  G11C16/14 ,  H01L29/42332 ,  H01L29/7885 ,  H01L29/792

摘要： A nonvolatile memory cell is provided. The memory cell comprises a storage transistor and an injector in a semiconductor substrate of a p-type conductivity. The injector comprises a first region of the p-type conductivity and a second region of an n-type conductivity. The storage transistor comprises a source, a drain, a channel, a charge storage region, and a control gate. The source and the drain have the p-type conductivity and are formed in a well of the n-type conductivity in the substrate with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel by a first insulator. The control gate is disposed over and insulated from the charge storage region by a second insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the first insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the first insulator onto the charge storage region.

摘要翻译： 提供非易失性存储单元。 存储单元包括p型导电性的半导体衬底中的存储晶体管和注入器。 注射器包括p型导电性的第一区域和n型导电性的第二区域。 存储晶体管包括源极，漏极，沟道，电荷存储区域和控制栅极。 源极和漏极具有p型导电性，并且形成在衬底中的n型导电性的阱中，阱之间的沟道被限定。 电荷存储区域通过第一绝缘体设置在沟道之上并与沟道绝缘。 控制栅极通过第二绝缘体设置在电荷存储区域之上并与电荷存储区域绝缘。 还提供了操作存储单元的方法，包括用于将电子从通道中通过第一绝缘体注入到电荷存储区上的装置，以及用于将来自注射器的孔穿过阱通过穿过第一绝缘体的沟道注入到电荷存储区上的装置。