公开(公告)号：US09431550B2

公开(公告)日：2016-08-30

申请号：US13308375

申请日：2011-11-30

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L27/12 ,  H01L29/76 ,  H01L29/866 ,  H01L27/06 ,  H01L27/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

公开(公告)号：US07544545B2

公开(公告)日：2009-06-09

申请号：US11322040

申请日：2005-12-28

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N−(P−) type epitaxial region on a N+(P+) type substrate and forming a trench in the N−(P−) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+(N+) type doped polysilicon region and N+(P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.

摘要翻译： 本发明的实施例包括制造沟槽多晶硅二极管的方法。 该方法包括在N +（P +）型衬底上形成N-（P-）型外延区，并在N-（P-）型外延区中形成沟槽。 该方法还包括在沟槽中形成绝缘层，并用形成沟槽顶表面的多晶硅填充沟槽。 该方法还包括在沟槽中形成P +（N +）型掺杂多晶硅区域和N +（P +）型掺杂多晶硅区域，并在沟槽中形成二极管，其中二极管的一部分低于沟槽的顶表面。

公开(公告)号：US20120068178A1

公开(公告)日：2012-03-22

申请号：US13308375

申请日：2011-11-30

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

摘要翻译： 本发明的实施例包括制造沟槽晶体管的方法。 该方法包括形成第一导电类型的衬底并注入第二导电类型的掺杂剂，形成衬底的体区。 所述方法还包括在所述体区域中形成沟槽，并且在所述沟槽中以及在所述主体区域上沉积绝缘层，其中所述绝缘层对准所述沟槽。 该方法还包括用形成沟槽顶表面的多晶硅填充沟槽，并在体区中形成二极管，其中二极管的一部分低于沟槽的顶表面。

公开(公告)号：US09306056B2

公开(公告)日：2016-04-05

申请号：US12610148

申请日：2009-10-30

申请人： Deva Pattanayak ,  King Owyang ,  Mohammed Kasem ,  Kyle Terrill ,  Reuven Katraro ,  Kuo-In Chen ,  Calvin Choi ,  Qufei Chen ,  Ronald Wong ,  Kam Hong Lui ,  Robert Xu

发明人： Deva Pattanayak ,  King Owyang ,  Mohammed Kasem ,  Kyle Terrill ,  Reuven Katraro ,  Kuo-In Chen ,  Calvin Choi ,  Qufei Chen ,  Ronald Wong ,  Kam Hong Lui ,  Robert Xu

IPC分类号： H01L23/48 ,  H01L29/78 ,  H01L23/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/45

CPC分类号： H01L29/7809 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/06051 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

摘要翻译： 半导体器件（例如，倒装芯片）包括通过中间层与漏极接触分离的衬底层。 通过中间层的沟槽状馈通元件用于在器件工作时电连接漏极接触和衬底层。

公开(公告)号：US20110101525A1

公开(公告)日：2011-05-05

申请号：US12610148

申请日：2009-10-30

申请人： Deva Pattanayak ,  King Owyang ,  Mohammed Kasem ,  Kyle Terrill ,  Reuven Katraro ,  Kuo-In Chen ,  Calvin Choi ,  Qufei Chen ,  Ronald Wong ,  Kam Hong Lui ,  Robert Xu

发明人： Deva Pattanayak ,  King Owyang ,  Mohammed Kasem ,  Kyle Terrill ,  Reuven Katraro ,  Kuo-In Chen ,  Calvin Choi ,  Qufei Chen ,  Ronald Wong ,  Kam Hong Lui ,  Robert Xu

IPC分类号： H01L23/48 ,  H01L23/488 ,  H01L21/768

CPC分类号： H01L29/7809 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/06051 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

摘要翻译： 半导体器件（例如，倒装芯片）包括通过中间层与漏极接触分离的衬底层。 通过中间层的沟槽状馈通元件用于在器件工作时电连接漏极接触和衬底层。

公开(公告)号：US07612431B2

公开(公告)日：2009-11-03

申请号：US12009379

申请日：2008-01-17

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L23/58

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

摘要翻译： 本发明的实施例包括制造沟槽晶体管的方法。 该方法包括形成第一导电类型的衬底并注入第二导电类型的掺杂剂，形成衬底的体区。 所述方法还包括在所述体区域中形成沟槽，并且在所述沟槽中以及在所述主体区域上沉积绝缘层，其中所述绝缘层对准所述沟槽。 该方法还包括用形成沟槽顶表面的多晶硅填充沟槽，并在体区中形成二极管，其中二极管的一部分低于沟槽的顶表面。

公开(公告)号：US08072013B1

公开(公告)日：2011-12-06

申请号：US12611865

申请日：2009-11-03

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

摘要翻译： 本发明的实施例包括制造沟槽晶体管的方法。 该方法包括形成第一导电类型的衬底并注入第二导电类型的掺杂剂，形成衬底的体区。 所述方法还包括在所述体区域中形成沟槽，并且在所述沟槽中以及在所述主体区域上沉积绝缘层，其中所述绝缘层对准所述沟槽。 该方法还包括用形成沟槽顶表面的多晶硅填充沟槽，并在体区中形成二极管，其中二极管的一部分低于沟槽的顶表面。

公开(公告)号：US20080135872A1

公开(公告)日：2008-06-12

申请号：US12009379

申请日：2008-01-17

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L29/74

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

摘要翻译： 本发明的实施例包括制造沟槽晶体管的方法。 该方法包括形成第一导电类型的衬底并注入第二导电类型的掺杂剂，形成衬底的体区。 所述方法还包括在所述体区域中形成沟槽，并且在所述沟槽中以及在所述主体区域上沉积绝缘层，其中所述绝缘层对准所述沟槽。 该方法还包括用形成沟槽顶表面的多晶硅填充沟槽，并在体区中形成二极管，其中二极管的一部分低于沟槽的顶表面。

公开(公告)号：US20070145411A1

公开(公告)日：2007-06-28

申请号：US11322040

申请日：2005-12-28

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L29/74

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N− (P−) type epitaxial region on a N+ (P+) type substrate and forming a trench in the N− (P−) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+ (N+) type doped polysilicon region and N+ (P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.

摘要翻译： 本发明的实施例包括制造沟槽多晶硅二极管的方法。 该方法包括在N +（P +）型衬底上形成N-（P-）型外延区，并在N-（P-）型外延区中形成沟槽。 该方法还包括在沟槽中形成绝缘层，并用形成沟槽顶表面的多晶硅填充沟槽。 该方法还包括在沟槽中形成P +（N +）型掺杂多晶硅区域和N +（P +）型掺杂多晶硅区域，并在沟槽中形成二极管，其中二极管的一部分低于沟槽的顶表面。

公开(公告)号：US20080157281A1

公开(公告)日：2008-07-03

申请号：US12069712

申请日：2008-02-11

申请人： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

发明人： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

IPC分类号： H01L29/36

CPC分类号： H01L29/0878 ,  H01L29/167 ,  H01L29/7813

摘要： Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.

摘要翻译： 超低漏源电阻功率MOSFET。 根据本发明的实施例，半导体器件包括多个沟槽功率MOSFET。 多个沟槽功率MOSFET形成在第二外延层中。 第二外延层形成为与第一外延层相邻并邻接。 第一外延层与高度掺杂有红磷的衬底相邻并邻接地形成。 新颖的红色磷掺杂衬底能够实现所需的低漏源电阻。