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公开(公告)号：US07206925B1
公开(公告)日：2007-04-17
申请号：US09643895
申请日：2000-08-18
Applicant: Quinn A. Jacobson , Chiao-Mei Chuang
Inventor： Quinn A. Jacobson , Chiao-Mei Chuang
IPC: G06F9/34
CPC classification number: G06F9/30138 , G06F9/30043 , G06F9/30116 , G06F9/30127 , G06F9/383
Abstract: A processor is defined by a new architectural feature called a Backing Register File, where a Backing Register File is a set of randomly accessible registers capable of holding values, and further are directly connected to the processor's register files. The processor's register files are in turn connected to the processor's execution units. A Backing Register File is visible and controllable by users, allowing them to make use of a larger local address space increasing execution unit throughput thereby, while not changing the size of the processor's register files themselves.
Abstract translation: 处理器由称为备份寄存器文件的新架构特征定义，其中备份寄存器文件是能够保存值的一组可随机访问的寄存器，并且还直接连接到处理器的寄存器文件。 处理器的寄存器文件又连接到处理器的执行单元。 备份寄存器文件是可见和可控的用户，允许他们利用更大的本地地址空间增加执行单位吞吐量，而不改变处理器的寄存器文件本身的大小。
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公开(公告)号：US06757807B1
公开(公告)日：2004-06-29
申请号：US09642075
申请日：2000-08-18
Applicant: Quinn A. Jacobson , Chiao-Mei Chuang
Inventor： Quinn A. Jacobson , Chiao-Mei Chuang
IPC: G06F1500
CPC classification number: G06F9/3891 , G06F9/3012 , G06F9/30138 , G06F9/3826 , G06F9/3836 , G06F9/3885
Abstract: A processor comprising a new architectural feature called a Register Domain, where a Register Domain has a register file, at least one execution unit, and coupling circuitry between the two. A processor will typically have a plurality of Register Domains, and Register Domains may have different types of execution units within them. Individual Register Domains will be visible to a user.
Abstract translation: 一种处理器，包括称为寄存器域的新架构特征，其中寄存器域具有寄存器文件，至少一个执行单元和两者之间的耦合电路。 处理器通常具有多个注册域，注册域可以具有不同类型的执行单元。 个别注册域将对用户可见。
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3.发明授权Logical power throttling of instruction decode rate for successive time periods 有权连续时间段的逻辑功率节制指令解码速率公开(公告)号：US08745419B2
公开(公告)日：2014-06-03
申请号：US13529761
申请日：2012-06-21
Applicant: Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
Inventor： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
CPC classification number: G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
Abstract: A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
Abstract translation: 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。
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4.发明授权Method and message handling hardware structure for virtualization and isolation of partitions 有权用于虚拟化和隔离隔离的方法和消息处理硬件结构公开(公告)号：US08707332B2
公开(公告)日：2014-04-22
申请号：US13588191
申请日：2012-08-17
Applicant: Ashley Saulsbury , Quinn A. Jacobson
Inventor： Ashley Saulsbury , Quinn A. Jacobson
IPC: G06F9/54
CPC classification number: G06F9/545 , G06F9/45558 , G06F9/546 , G06F2209/548
Abstract: A computer-based method configures a hardware circuit to transfer a message to a message queue in an operating system. The hardware circuit is used to transfer a message to the message queue in the operating system without requiring use of either the operating system or a hypervisor associated with the operating system. The using the hardware circuit uses a logical identifier associated with the message to select an entry in a mapping table of the hardware circuit. A value in the entry in the mapping table is used to select an entry in an action table. The entry in the action table is used to determine a tail pointer for the message queue. The hardware circuit appends the message to a location indicted by the tail pointer without requiring cycles of a hypervisor associated with the strand.
Abstract translation: 基于计算机的方法配置硬件电路以将消息传送到操作系统中的消息队列。 硬件电路用于将消息传送到操作系统中的消息队列，而不需要使用操作系统或与操作系统相关联的管理程序。 使用硬件电路使用与消息相关联的逻辑标识符来选择硬件电路的映射表中的条目。 映射表中条目中的值用于在操作表中选择一个条目。 动作表中的条目用于确定消息队列的尾部指针。 硬件电路将消息附加到由尾部指针指示的位置，而不需要与该线束相关联的管理程序的周期。
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5.发明申请METHOD AND MESSAGE HANDLING HARDWARE STRUCTURE FOR VIRTUALIZATION AND ISOLATION OF PARTITIONS 有权用于虚拟化和隔离的方法和消息处理硬件结构公开(公告)号：US20120317588A1
公开(公告)日：2012-12-13
申请号：US13588191
申请日：2012-08-17
Applicant: Ashley Saulsbury , Quinn A. Jacobson
Inventor： Ashley Saulsbury , Quinn A. Jacobson
IPC: G06F9/455
CPC classification number: G06F9/545 , G06F9/45558 , G06F9/546 , G06F2209/548
Abstract: A computer-based method configures a hardware circuit to transfer a message to a message queue in an operating system. The hardware circuit is used to transfer a message to the message queue in the operating system without requiring use of either the operating system or a hypervisor associated with the operating system. The using the hardware circuit uses a logical identifier associated with the message to select an entry in a mapping table of the hardware circuit. A value in the entry in the mapping table is used to select an entry in an action table. The entry in the action table is used to determine a tail pointer for the message queue. The hardware circuit appends the message to a location indicted by the tail pointer without requiring cycles of a hypervisor associated with the strand.
Abstract translation: 基于计算机的方法配置硬件电路以将消息传送到操作系统中的消息队列。 硬件电路用于将消息传送到操作系统中的消息队列，而不需要使用操作系统或与操作系统相关联的管理程序。 使用硬件电路使用与消息相关联的逻辑标识符来选择硬件电路的映射表中的条目。 映射表中的条目中的值用于在操作表中选择一个条目。 动作表中的条目用于确定消息队列的尾部指针。 硬件电路将消息附加到由尾部指针指示的位置，而不需要与该线束相关联的管理程序的周期。
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Patent Agency Ranking
公开(公告)号：US07882339B2
公开(公告)日：2011-02-01
申请号：US11165639
申请日：2005-06-23
Applicant: Quinn A. Jacobson , Hong Wang , John Shen , Gautham N. Chinya , Per Hammarlund , Xiang Zou , Bryant Bigbee , Shivnandan D. Kaushik
Inventor： Quinn A. Jacobson , Hong Wang , John Shen , Gautham N. Chinya , Per Hammarlund , Xiang Zou , Bryant Bigbee , Shivnandan D. Kaushik
CPC classification number: G06F9/526 , G06F9/30087 , G06F9/30101 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861
Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.
Abstract translation: 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。
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7.发明授权Start transactional execution (STE) instruction to support transactional program execution 有权启动事务执行（STE）指令以支持事务性程序执行公开(公告)号：US07500086B2
公开(公告)日：2009-03-03
申请号：US11296599
申请日：2005-12-06
Applicant: Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
Inventor： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
CPC classification number: G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
Abstract: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
Abstract translation: 本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。 在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。 在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。
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公开(公告)号：US07418577B2
公开(公告)日：2008-08-26
申请号：US10637169
申请日：2003-08-08
Applicant: Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
Inventor： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
IPC: G06F9/00
CPC classification number: G06F9/3863 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857
Abstract: One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.
Abstract translation: 本发明的一个实施例提供一种支持执行失败指令的系统，其终止指令块的事务执行。 在操作期间，系统促进程序内的指令块的事务执行，其中在事务执行期间所做的更改不会被提交到处理器的体系结构状态，直到事务执行成功完成。 如果在此事务执行期间遇到失败指令，则系统终止事务执行，而不将事务执行的结果提交给处理器的体系结构状态。
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9.发明授权Logically partitioning different classes of TLB entries within a single caching structure 有权在单个缓存结构中逻辑分区不同类别的TLB条目公开(公告)号：US07293157B1
公开(公告)日：2007-11-06
申请号：US10997394
申请日：2004-11-24
Applicant: Vipul Y. Parikh , Quinn A. Jacobson
Inventor： Vipul Y. Parikh , Quinn A. Jacobson
IPC: G06F12/08
CPC classification number: G06F12/1027 , G06F12/0864 , G06F2212/601
Abstract: One embodiment of the present invention provides a system that logically partitions different classes of translation lookaside buffer (TLB) entries within a single caching structure. Upon receiving a request to lookup an address translation, the system applies a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside. If the corresponding location contains a TLB entry for the request, the system returns data from the TLB entry to facilitate the address translation. This hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure. In this way, the single caching structure can accommodate different classes of TLB entries at the same time.
Abstract translation: 本发明的一个实施例提供了一种在单个高速缓存结构内逻辑地分割不同类别的翻译后备缓冲器（TLB）条目的系统。 在接收到查找地址转换的请求时，系统对与请求相关联的参数应用散列函数，以确定单个缓存结构中对应于该请求的TLB条目可以驻留的位置。 如果对应的位置包含该请求的TLB条目，系统将从TLB条目返回数据，以方便地址转换。 该哈希函数分割单个缓存结构，以便将不同类别的TLB条目映射到单个缓存结构的单独分区。 以这种方式，单个缓存结构可以同时容纳不同类别的TLB条目。
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公开(公告)号：US20070226467A1
公开(公告)日：2007-09-27
申请号：US11425869
申请日：2006-06-22
Applicant: Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
Inventor： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC: G06F9/30
CPC classification number: G06F9/3867 , G06F9/3836 , G06F9/384 , G06F9/3857
Abstract: A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
Abstract translation: 一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。 该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。
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