公开(公告)号：US20130235649A1

公开(公告)日：2013-09-12

申请号：US13788233

申请日：2013-03-07

Applicant: RAMBUS INC.

Inventor： Eric Lindstadt ,  Brent Steven Haukness ,  J. James Tringali

IPC: G11C13/00 ,  G11C29/38

CPC classification number: G11C13/0035 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/00 ,  G11C29/38 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2029/5002 ,  G11C2213/79

Abstract: Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells.

Abstract translation: 公开了包括多个电阻变化存储单元的存储器，其包括至少第一组和第二组存储单元，以及比较电路，被配置为进行与第一组存储单元的剩余耐久性的直接相对比较 第二组记忆单元的剩余耐力。

公开(公告)号：US09515204B2

公开(公告)日：2016-12-06

申请号：US13804334

申请日：2013-03-14

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  Eric Lindstadt ,  Jun Kim

IPC: G06F12/02 ,  H01L31/0236 ,  G06F12/00 ,  G06F13/16

CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1684 ,  G06F13/372 ,  Y02D10/14

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

Abstract translation: 存储器控制器包括用于将存储器命令发送到与存储器控制器相关联的多个存储器件的命令接口。 存储器控制器还包括确认界面，用于通过耦合在存储器控制器和多个存储器件之间的共享确认链路从多个存储器设备接收确认状态分组，该确认状态分组指示该命令是否被多个 的存储器件。 此外，存储器控制器包括存储器控制器核心，用于对确认状态分组进行解码，以识别对应于多个存储器设备中的每一个的确认状态分组的一部分。