公开(公告)号：US20120326123A1

公开(公告)日：2012-12-27

申请号：US13545358

申请日：2012-07-10

申请人： RAVI PILLARISETTY ,  Mantu Hudait ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Robert Chau

发明人： RAVI PILLARISETTY ,  Mantu Hudait ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Robert Chau

IPC分类号： H01L29/02

CPC分类号： H01L29/66977 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/365 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/7781

摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20140175379A1

公开(公告)日：2014-06-26

申请号：US13721759

申请日：2012-12-20

申请人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITIKA GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

发明人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITIKA GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC分类号： H01L29/06

CPC分类号： H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

摘要翻译： 本发明的实施例包括外延层，其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线，翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线，鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部，底部和侧壁的“全向栅极”结构。 本文描述了其它实施例。

公开(公告)号：US20140175509A1

公开(公告)日：2014-06-26

申请号：US13723563

申请日：2012-12-21

申请人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITI GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

发明人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITI GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC分类号： H01L29/06

CPC分类号： H01L29/7391 ,  H01L29/0676 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66356 ,  H01L29/66393 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7436 ,  H01L29/785

摘要： An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.

摘要翻译： 一个实施例涉及在衬底上形成EPI膜，其中EPI膜具有与衬底不同的晶格常数。 EPI膜和衬底可以包括不同的材料以共同形成具有例如Si和/或SiGe衬底和III-V或IV膜的异质外延装置。 EPI膜可以是多个EPI层或膜中的一个，并且膜可以包括彼此不同的材料并且可以直接彼此接触。 此外，在掺杂浓度和/或掺杂极性方面，多个EPI层可以与另一个不同地被掺杂。 一个实施例包括产生水平取向的异质外延结构。 另一实施例包括垂直取向的异质外延结构。 异质外延结构可以包括例如双极结型晶体管，异质结双极晶体管，晶闸管和隧道场效应晶体管等。 本文描述了其它实施例。

公开(公告)号：US20140175378A1

公开(公告)日：2014-06-26

申请号：US13722746

申请日：2012-12-20

申请人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van Le ,  Matthew Metz ,  Jack Kavalieros ,  RAVI PILLARISETTY ,  Sanaz Gardner ,  SANSAPTAK DASGUPTA ,  Willy Rachmady ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  Gilbert Dewey ,  Marc French ,  JESSICA KACHIAN ,  SATYARTH SURI ,  Robert Chau

发明人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van Le ,  Matthew Metz ,  Jack Kavalieros ,  RAVI PILLARISETTY ,  Sanaz Gardner ,  SANSAPTAK DASGUPTA ,  Willy Rachmady ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  Gilbert Dewey ,  Marc French ,  JESSICA KACHIAN ,  SATYARTH SURI ,  Robert Chau

IPC分类号： H01L21/20 ,  H01L21/764

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/76232

摘要： An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.

摘要翻译： 实施例包括将材料沉积到衬底上，其中材料包括与衬底（例如Si衬底上的III-V或IV外延（EPI）材料）不同的晶格常数。 一个实施例包括形成在沟槽内的EPI层，其具有随着沟槽向上延伸而变窄的壁。 实施例包括使用多个生长温度在沟槽内形成的EPI层。 当温度变化时，在EPI层中形成的缺陷屏障在沟槽内和缺陷屏障之下包含缺陷。 缺陷屏障之上和沟槽内的EPI层相对无缺陷。 一个实施方案包括在沟槽内退火以引发缺陷湮灭的EPI层。 一个实施例包括形成在沟槽内并覆盖有相对无缺陷的EPI层（仍包含在沟槽中）的EPI超晶格。 本文描述了其它实施例。

公开(公告)号：US20140175512A1

公开(公告)日：2014-06-26

申请号：US13722824

申请日：2012-12-20

申请人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITI GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

发明人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITI GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC分类号： H01L29/78

CPC分类号： H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/785

摘要： An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.

摘要翻译： 一个实施例使用非常薄的层纳米结构（例如，Si或SiGe鳍）作为模板来生长晶体，非晶格匹配的外延（EPI）层。 在一个实施方案中，纳米结构和EPI层之间的体积比使得EPI层比纳米结构厚。 在一些实施例中，在纳米结构和EPI之间包括非常薄的桥接层。 一个实施例包括一个CMOS器件，其中覆盖翅片（或一旦被覆盖的翅片）的EPI层彼此相反地极化。 一个实施例包括一个CMOS器件，其中覆盖翅片（或一旦被覆盖的翅片）的EPI层与覆盖翅片（或一旦被覆盖的翅片）的桥接层相反地偏振。 因此，从EPI层转移到纳米结构（剩下的存在或去除）的缺陷中公开了各种实施例。 本文描述了其它实施例。

公开(公告)号：US20110147712A1

公开(公告)日：2011-06-23

申请号：US12646589

申请日：2009-12-23

申请人： MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY

发明人： MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY

IPC分类号： H01L29/772 ,  H01L29/12 ,  H01L21/335

CPC分类号： H01L29/66636 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7784

摘要： A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.

摘要翻译： 公开了一种量子阱器件及其制造方法。 在一个实施例中，量子阱结构包括覆盖在衬底上的量子阱区域和包括与量子阱区域的电荷载流子的导电性相反的导电性的掺杂剂的远程计数器掺杂。 远程计数器掺杂被结合在量子阱区域附近，用于与量子阱沟道交换移动载流子，从而减小截止状态的漏电流。 在另一个实施例中，量子阱器件包括量子阱结构，其包括远程反相掺杂，覆盖量子阱结构的一部分的栅极区域和与栅极区域相邻的源极和漏极区域。 量子阱器件还可以包括包含与量子阱沟道相同导电性的掺杂剂的远程δ掺杂。

公开(公告)号：US20180062077A1

公开(公告)日：2018-03-01

申请号：US15529907

申请日：2014-12-24

申请人： NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  PRASHANT MAJHI ,  UDAY SHAH ,  RYAN E ARCH ,  MARKUS KUHN ,  JUSTIN S. BROCKMAN ,  HUIYING LIU ,  ELIJAH V KARPOV ,  KAAN OGUZ

发明人： NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  PRASHANT MAJHI ,  UDAY SHAH ,  RYAN E ARCH ,  MARKUS KUHN ,  JUSTIN S. BROCKMAN ,  HUIYING LIU ,  ELIJAH V KARPOV ,  KAAN OGUZ

IPC分类号： H01L45/00

摘要： Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

公开(公告)号：US20170271583A1

公开(公告)日：2017-09-21

申请号：US15528674

申请日：2014-12-18

申请人： PRASHANT MAJHI ,  RAVI PILLARISETTY ,  NILOY MUKHERJEE ,  UDAY SHAH ,  ELIJAH V. KARPOV ,  BRIAN S. DOYLE ,  ROBERT S. CHAU

发明人： PRASHANT MAJHI ,  RAVI PILLARISETTY ,  NILOY MUKHERJEE ,  UDAY SHAH ,  ELIJAH V. KARPOV ,  BRIAN S. DOYLE ,  ROBERT S. CHAU

IPC分类号： H01L45/00

CPC分类号： H01L45/122 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1641

摘要： Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.