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    SOI SRAM HAVING WELL REGIONS WITH OPPOSITE CONDUCTIVITY
    1.
    发明申请
    SOI SRAM HAVING WELL REGIONS WITH OPPOSITE CONDUCTIVITY 有权
    具有OPPOSITE电导率的良好区域的SOI SRAM

    公开(公告)号：US20150221668A1

    公开(公告)日：2015-08-06

    申请号：US14615336

    申请日：2015-02-05

    Applicant: Renesas Electronics Corporation

    Inventor： Katsuyuki HORITA ,  Toshiaki IWAMATSU ,  Hideki MAKIYAMA

    IPC: H01L27/12 ,  H01L27/11 ,  H01L27/092

    CPC classification number: H01L27/1203 ,  G11C11/412 ,  H01L21/2652 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/78648

    Abstract: A semiconductor device with an SRAM memory cell having improved characteristics.Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

    Abstract translation: 具有SRAM存储单元的具有改进特性的半导体器件。 在其中放置包括SRAM的驱动器晶体管的有源区域之下，经由绝缘层提供被元件隔离区域包围的n型背栅极区域。 它耦合到驱动晶体管的栅极电极。 p型阱区域设置在n型背栅区域的下方，并且至少部分延伸到比元件隔离区域更深的位置。 它固定在接地电位。 这样的结构使得可以在晶体管导通时控制晶体管的阈值电位为高，并且当晶体管截止时，晶体管的阈值电位变低; 并且控制以便不对p阱区域和n型背栅极区域之间的PN结施加正向偏压。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20130119469A1

    公开(公告)日：2013-05-16

    申请号：US13675682

    申请日：2012-11-13

    Applicant: Renesas Electronics Corporation

    Inventor： Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA

    IPC: H01L27/088 ,  H01L29/78

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1207 ,  H01L29/78648

    Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.

    Semiconductor Device
    6.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20160118407A1

    公开(公告)日：2016-04-28

    申请号：US14920823

    申请日：2015-10-22

    Applicant: Renesas Electronics Corporation

    Inventor： Hideki MAKIYAMA

    IPC: H01L27/12

    CPC classification number: H01L27/1203 ,  H01L27/1104

    Abstract: In a semiconductor device having an SRAM memory cell, its reliability is improved. In the semiconductor device having the SRAM memory cell, electrically-independent four semiconductor regions functioning as hack gates are provided below two load transistors and two driver transistors, so that threshold voltages for the load transistors and driver transistors are controlled. And, the two n-type semiconductor regions provided below the two load transistors are electrically isolated from each other by a p-type semiconductor region.

    Abstract translation: 在具有SRAM存储单元的半导体器件中，其可靠性得到改善。 在具有SRAM存储单元的半导体器件中，在两个负载晶体管和两个驱动晶体管之下设置电气独立的用作黑门的四个半导体区域，从而控制负载晶体管和驱动晶体管的阈值电压。 并且，设置在两个负载晶体管下方的两个n型半导体区域通过p型半导体区域彼此电隔离。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150008522A1

    公开(公告)日：2015-01-08

    申请号：US14495178

    申请日：2014-09-24

    Applicant: Renesas Electronics Corporation

    Inventor： Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA

    IPC: H01L27/12 ,  H01L27/11

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1207 ,  H01L29/78648

    Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.

    Abstract translation: 在包括SRAM存储单元的半导体器件的特性中实现了改进。 在其中设置形成SRAM的存取晶体管的有源区域中，p型半导体区域经由绝缘层设置，使得其底部和侧部与n型半导体区域接触。 因此，p型半导体区域与n型半导体区域pn隔离，并且存取晶体管的栅电极耦合到p型半导体区域。 耦合是通过共享插头实现的，该共用插头是从存取晶体管的栅极电极延伸到p型半导体区域上的不连续的导电膜。 结果，当存取晶体管处于导通状态时，用作背栅的p型半导体区域中的电位同时增加，以允许晶体管的导通电流增加。

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