公开(公告)号：US20240006275A1

公开(公告)日：2024-01-04

申请号：US18307394

申请日：2023-04-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Noriko NUMATA ,  Koichi HASEGAWA ,  Tatsuaki TSUKUDA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49562 ,  H01L23/49513 ,  H01L23/3121 ,  H01L24/40 ,  H01L24/84 ,  H01L24/48 ,  H01L24/45 ,  H01L21/56 ,  H01L2224/40175 ,  H01L2224/32245 ,  H01L24/32 ,  H01L2224/73263 ,  H01L24/73 ,  H01L2224/84897 ,  H01L2224/48175 ,  H01L2224/45147 ,  H01L2224/73221

Abstract: A source pad electrically coupled with a source of a MOSFET of a semiconductor chip and located at a position below a lead in cross-sectional view is electrically connected with the lead for source via a conductive member bonded to the source pad and a wire bonded to the conductive member.

公开(公告)号：US20170207535A1

公开(公告)日：2017-07-20

申请号：US15324650

申请日：2014-07-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuaki TSUKUDA ,  Hideki SASAKI

IPC: H01Q7/00 ,  H01Q3/24 ,  H01Q1/24

CPC classification number: H01Q7/00 ,  H01Q1/24 ,  H01Q3/24 ,  H02J50/27 ,  H02J50/80

Abstract: A loop antenna 1 includes: a first electrode terminal 2c; a second electrode terminal 2d arranged to make a pair with the first electrode terminal 2c; and a loop-shaped member 2 which has one end connected to the first electrode terminal 2c and the other end connected to the second electrode terminal 2d, is wound a plurality of times, and is made of a conductive material. The first electrode terminal 2c and the second electrode terminal 2d are arranged so as to make a pair with respect to a center line 3 of the loop-shaped member 2. Further, the loop-shaped member 2 includes a first loop-shaped member 2a, a second loop-shaped member 2b, and an intersection part 2e. The intersection part 2e is arranged on the center line 3 in a plan view, and the loop-shaped member 2 is continuously connected and formed to be symmetrical with respect to the center line 3.

公开(公告)号：US20240164118A1

公开(公告)日：2024-05-16

申请号：US18479327

申请日：2023-10-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TSUCHIYAMA ,  Tatsuaki TSUKUDA

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/16

CPC classification number: H10B80/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/48229 ,  H01L2224/48245 ,  H01L2224/48265 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83095 ,  H01L2224/92147 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106

Abstract: A semiconductor device includes: a base material having a first terminal; a semiconductor chip having a first electrode pad electrically connected with the first terminal, a second electrode pad to which a power supply potential is to be supplied, and a third electrode pad to which a reference potential is to be supplied, and mounted on the base material via a first member; a chip capacitor having a first electrode and a second electrode, and mounted on the semiconductor chip via a second member; a first wire electrically connecting the first electrode pad with the first terminal; a second wire electrically connecting the second electrode pad with the first electrode without going through the base material; and a third wire electrically connecting the third electrode pad with the second electrode without going through the base material.

公开(公告)号：US20230144840A1

公开(公告)日：2023-05-11

申请号：US17894572

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki SASAKI ,  Tatsuaki TSUKUDA ,  Hiroya SHIMOYAMA

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/481 ,  H01L23/49513 ,  H01L24/29 ,  H01L25/074 ,  H01L2224/29139

Abstract: A semiconductor device includes a semiconductor chip hazing a non-overlapping region in which a source pad for main transistor and a clip do not overlap with each other. At this time, a sense transistor is arranged in a region of the non-overlapping region, which is located between a first portion of the clip and a first short side of the source pad for main transistor in a plan view.

公开(公告)号：US20160156231A1

公开(公告)日：2016-06-02

申请号：US14896867

申请日：2013-06-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki SHIBUYA ,  Hideki SASAKI ,  Tatsuaki TSUKUDA ,  Tadashi SHIMIZU ,  Masahiro DOBASHI ,  Shinji NISHIZONO ,  Hiroko KUBOTA

IPC: H02J50/12 ,  H04B5/00

CPC classification number: H02J50/12 ,  H02J7/025 ,  H02J50/80 ,  H04B5/0037 ,  H04B5/0081

Abstract: In a communication control device in which an antenna electrode having an antenna connected thereto, a power supply circuit, and a communication circuit are mounted on a mounting board, the antenna electrode is disposed at one corner portion on a principal surface of the mounting board, the communication circuit is disposed on a side of a first side of the principal surface that shares the corner portion, and the power supply circuit is disposed on a side of a second side facing the first side. Further, a first signal path connecting the antenna electrode and the communication circuit extends along the first side, and a second signal path connecting the antenna electrode and the power supply circuit extends along a third side that shares the corner portion and is perpendicular to the first side.

Abstract translation: 在其中连接有天线的天线电极，电源电路和通信电路安装在安装板上的通信控制装置中，天线电极设置在安装板的主表面上的一个角部， 通信电路设置在共享角部的主表面的第一侧的一侧，并且电源电路设置在面向第一侧的第二侧的一侧。 此外，连接天线电极和通信电路的第一信号路径沿着第一侧延伸，并且连接天线电极和电源电路的第二信号路径沿共享角部的第三侧延伸并垂直于第一 侧。

公开(公告)号：US20240153854A1

公开(公告)日：2024-05-09

申请号：US18358400

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TSUCHIYA ,  Tatsuaki TSUKUDA

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor device includes a wiring substrate including a plurality of wiring layers, and a semiconductor chip including a first analog circuit. A power supply potential pattern capable of supplying a first power supply potential to the first analog circuit and a reference potential pattern capable of supplying a first reference potential to the first analog circuit are electrically connected with the first analog circuit. The power supply potential pattern is provided in a first wiring layer which is the nearest to a lower surface of the wiring substrate among the plurality of wiring layers. The reference potential pattern is provided in a second wiring layer which is the next nearest to the lower surface after the first wiring layer. The power supply potential pattern and the reference potential pattern extend in the same direction as each other while mutually overlapping with each other in transparent plan view.

公开(公告)号：US20230062318A1

公开(公告)日：2023-03-02

申请号：US17872543

申请日：2022-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuaki TSUKUDA

IPC: H01L23/498 ,  H01L23/00

Abstract: A performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip, and a clip mounted on the semiconductor chip via a silver paste. Here, the semiconductor chip includes a passivation film having an opening, a source pad of a main transistor having a portion exposed from the passivation film at the opening, and a wall portion provided on the passivation film so as to surround the source pad in a plan view. At this time, a whole of the portion (exposed surface) of the source pad, which is exposed from the passivation film, is covered with the silver paste. Further, in the plan view, the silver paste connecting the source pad with the clip is positioned inside of an area surrounded by the wall portion, without overflowing.

公开(公告)号：US20190333866A1

公开(公告)日：2019-10-31

申请号：US16378197

申请日：2019-04-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuaki TSUKUDA

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H03H7/065 ,  H02K11/22 ,  H02K11/33

Abstract: An electronic device includes a wiring board and a semiconductor device on the wiring board's main surface. The semiconductor device includes a semiconductor chip on a die pad sealed by a sealing body. A back surface of the die pad is directed to a main surface of the sealing body. A back surface of the sealing body faces the main surface of the wiring board. First and second electrodes are formed on the wiring board and in the sealing body, respectively. The second electrode is disposed in the back surface of the sealing body, and is bonded to a metal plate connecting a lead and a pad. A distance between the first and second electrodes is shorter than that between the metal plate and the first electrode. The first and second electrodes overlap each other in a plan view. A capacitor is composed of the first and second electrodes.

公开(公告)号：US20180295715A1

公开(公告)日：2018-10-11

申请号：US15762986

申请日：2015-11-30

Applicant: Renesas Electronics Corporation

Inventor： Tatsuaki TSUKUDA ,  Akihiro NAKAHARA

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01L25/16

Abstract: An electronic device according to one embodiment includes a wiring substrate, the wiring substrate having a first wiring connected to a first external terminal and a second wiring connected to a second external terminal and extending along the first wiring. Additionally, the above electronic device has a semiconductor device mounted on the above wiring substrate and electrically connected to each of the first and second wirings. Further, the above electronic device has a capacitor mounted on the above wiring substrate and electrically connected to the semiconductor device via each of the above first and second wirings. Furthermore, a distance between the above semiconductor device and capacitor is shorter than a distance between each of the above first and second external terminals and the above capacitor.

公开(公告)号：US20240304526A1

公开(公告)日：2024-09-12

申请号：US18437894

申请日：2024-02-09

Applicant: Renesas Electronics Corporation

Inventor： Masato NUMAZAKI ,  Youichi ABE ,  Tatsuaki TSUKUDA

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/06 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/32245 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265

Abstract: A semiconductor device includes: a die pad having an upper surface; a semiconductor chip; a plurality of leads; and a plurality of wires. The upper surface includes: a first region in which the semiconductor chip is mounted; a second region surrounding the first region in plan view; and a third region surrounding the second region in plan view. Also, a first metal film is provided in the second region. Further, a second metal film is provided in the third region. Here, in plan view, the semiconductor chip, the first meal film and the second metal film are spaced apart from one another. Also, the plurality of wires includes: a first wire bonded to each of a first electrode of the plurality of electrodes and the first metal film; and a second wire bonded to each of a first lead of the plurality of leads and the second metal film.