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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20160118394A1

    公开(公告)日：2016-04-28

    申请号：US14989999

    申请日：2016-01-07

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

    IPC: H01L27/115 ,  H01L27/092 ,  H01L21/8234

    CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

    Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

    Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20140242796A1

    公开(公告)日：2014-08-28

    申请号：US14079120

    申请日：2013-11-13

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

    IPC: H01L21/3105 ,  H01L27/105 ,  H01L21/8234

    CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

    Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

    Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件的半导体器件和制造方法

    公开(公告)号：US20140209996A1

    公开(公告)日：2014-07-31

    申请号：US14242500

    申请日：2014-04-01

    Applicant: Renesas Electronics Corporation

    Inventor： Koichi TOBA ,  Yasushi ISHII ,  Hiraku CHAKIHARA ,  Kota FUNAYAMA ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

    IPC: H01L29/792

    CPC classification number: H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

    Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20140302668A1

    公开(公告)日：2014-10-09

    申请号：US14308667

    申请日：2014-06-18

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA

    IPC: H01L21/02 ,  H01L21/265 ,  H01L29/66 ,  H01L29/40

    CPC classification number: H01L29/792 ,  H01L21/02214 ,  H01L21/26513 ,  H01L27/11573 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833

    Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.

    Abstract translation: 在包括非易失性存储器的半导体器件的性能方面实现了改进。 在分闸门非易失性存储器中，在存储栅电极和p型阱之间以及控制栅电极和存储栅电极之间形成绝缘膜。 在绝缘膜中，存储栅极电极的下表面和半导体衬底的上表面之间的部分具有氧化硅膜和置于氧化硅膜之间的氮化硅膜。 在绝缘膜中，控制栅电极的侧表面与存储栅电极的侧表面之间的部分由氧化硅膜形成，并且不具有氮化硅膜。

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