公开(公告)号：US20180047742A1

公开(公告)日：2018-02-15

申请号：US15672909

申请日：2017-08-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11563

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573

Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US20150171160A1

公开(公告)日：2015-06-18

申请号：US14636311

申请日：2015-03-03

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA ,  Yasushi ISHII ,  Toshikazu MATSUI ,  Takashi HASHIMOTO

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US20180301463A1

公开(公告)日：2018-10-18

申请号：US16012362

申请日：2018-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11563 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40117

Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US20180067793A1

公开(公告)日：2018-03-08

申请号：US15650282

申请日：2017-07-14

Applicant: Renesas Electronics Corporation

Inventor： Tomoya SAITO ,  Masamichi FUJITO ,  Koichi ANDO ,  Takashi HASHIMOTO

IPC: G06F11/07

CPC classification number: G06F11/0727 ,  G06F11/073 ,  G06F11/0793 ,  G06F2212/72 ,  G11C16/28 ,  G11C16/3431 ,  G11C29/50004

Abstract: The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.

公开(公告)号：US20130234289A1

公开(公告)日：2013-09-12

申请号：US13867213

申请日：2013-04-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA ,  Yasushi ISHII ,  Toshikazu MATSUI ,  Takashi HASHIMOTO

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US20190363095A1

公开(公告)日：2019-11-28

申请号：US16404095

申请日：2019-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto OMIZU ,  Takashi HASHIMOTO ,  Hideaki YAMAKOSHI

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L21/762 ,  H01L21/28 ,  H01L21/3065

Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.

公开(公告)号：US20180366475A1

公开(公告)日：2018-12-20

申请号：US16110555

申请日：2018-08-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L27/1157 ,  H01L29/66 ,  H01L29/423 ,  H01L29/792 ,  H01L23/528 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.

公开(公告)号：US20180329770A1

公开(公告)日：2018-11-15

申请号：US16032306

申请日：2018-07-11

Applicant: Renesas Electronics Corporation

Inventor： Tomoya SAITO ,  Masamichi FUJITO ,  KOICHI ANDO ,  Takashi HASHIMOTO

IPC: G06F11/07 ,  G11C16/34 ,  G11C29/50 ,  G11C16/28

CPC classification number: G06F11/0727 ,  G06F11/073 ,  G06F11/0793 ,  G06F2212/72 ,  G11C16/28 ,  G11C16/3431 ,  G11C29/50004

Abstract: A flash memory refreshes at a time before a read error might occur. A controller performs a first read operation and a second read operation using a sense amplifier. In the second read operation, a bit line potential controller draws out a potential of a bit line feeding the sense amplifier so that, if memory cell degradation has occurred, the degradation can be detected. For example, when first data read by the first read operation and second data read by the second read operation are determined to be different, the memory cell is refreshed.

公开(公告)号：US20180315702A1

公开(公告)日：2018-11-01

申请号：US15904346

申请日：2018-02-24

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L23/522 ,  H01L27/11517 ,  H01L49/02 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/40

Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

公开(公告)号：US20180286881A1

公开(公告)日：2018-10-04

申请号：US15871818

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11568 ,  H01L27/11573 ,  G11C11/40

Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.