公开(公告)号：US20170170100A1

公开(公告)日：2017-06-15

申请号：US15444773

申请日：2017-02-28

Applicant: Renesas Electronics Corporation

Inventor： Yuichi YATO ,  Hiroi OKA ,  Noriko OKUNISHI ,  Keita TAKADA

IPC: H01L23/495 ,  H01L23/24 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/565 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49805 ,  H01L23/49844 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/743 ,  H01L24/77 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40091 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/84205 ,  H01L2224/84439 ,  H01L2224/8501 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/92157 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

公开(公告)号：US20160204057A1

公开(公告)日：2016-07-14

申请号：US14901424

申请日：2013-07-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichi YATO ,  Hiroi OKA ,  Noriko OKUNISHI ,  Keita TAKADA

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/13

CPC classification number: H01L23/49513 ,  H01L21/565 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/49805 ,  H01L23/49844 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/743 ,  H01L24/77 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40091 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/84205 ,  H01L2224/84439 ,  H01L2224/8501 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/92157 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

Abstract translation: 根据实施例的半导体器件是半导体器件，其中安装在芯片安装部分上的半导体芯片被树脂密封，并且第一构件固定到半导体芯片的周边部分与周边部分之间的芯片安装表面侧 的芯片安装部分。 此外，第一构件被树脂密封。 此外，芯片安装部分的第一方向的第一部分的长度在平面图中大于半导体芯片沿第一方向的长度。

公开(公告)号：US20180277397A1

公开(公告)日：2018-09-27

申请号：US15900416

申请日：2018-02-20

Applicant: Renesas Electronics Corporation

Inventor： Shoji HASHIZUME ,  Keita TAKADA

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/544 ,  B29C45/14 ,  B29C45/00

CPC classification number: H01L21/565 ,  B29C45/0025 ,  B29C45/0046 ,  B29C45/14336 ,  B29C45/14655 ,  B29C2045/0027 ,  B29L2031/34 ,  H01L21/4825 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H02P27/06 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00

Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.

公开(公告)号：US20170179010A1

公开(公告)日：2017-06-22

申请号：US15380183

申请日：2016-12-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TAKADA ,  Tadatoshi DANNO

IPC: H01L23/495 ,  H01L23/00 ,  H04B5/00 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49861 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05014 ,  H01L2224/05639 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48108 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H04B5/0075 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

公开(公告)号：US20230402443A1

公开(公告)日：2023-12-14

申请号：US18303902

申请日：2023-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshihiro MASUMURA ,  Takamichi HOSOKAWA ,  Keita TAKADA

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/05 ,  H01L24/06 ,  H01L23/49575 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/73265 ,  H01L24/92 ,  H01L2224/92247 ,  H01L27/01

Abstract: A semiconductor device includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; second and third semiconductor chips mounted on the second chip mounting portion; and a sealing body for sealing them. Here, the third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. Also, the first coil is electrically connected with a first circuit formed in the first semiconductor chip, and the second coil is electrically connected with a second circuit formed in the second semiconductor chip. Also, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. Further, a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip.

公开(公告)号：US20230378032A1

公开(公告)日：2023-11-23

申请号：US18175805

申请日：2023-02-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kosuke KITAICHI ,  Masatoshi SUGIURA ,  Hideaki TAMIMOTO ,  Takehiko MAEDA ,  Keita TAKADA ,  Yoshitaka KYOUGOKU

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H02M7/00

CPC classification number: H01L23/49562 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49513 ,  H01L24/48 ,  H01L23/3142 ,  H01L21/565 ,  H01L23/4952 ,  H01L23/49582 ,  H02M7/003 ,  H01L24/83 ,  H01L2224/48247 ,  H01L2224/32245 ,  H01L2224/73265 ,  H01L2924/30101 ,  H01L2924/13091 ,  H01L2224/83862

Abstract: To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.

公开(公告)号：US20150069594A1

公开(公告)日：2015-03-12

申请号：US14539479

申请日：2014-11-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TAKADA ,  Tadatoshi DANNO ,  Hirokazu KATO

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.

Abstract translation: 可以防止半导体器件劣化。 半导体器件具有包括顶表面，底表面和多个侧表面的突片。 突片的每个侧表面具有连续到突片的底表面的第一部分，位于第一部分的外部并且延伸到突片的顶表面的第二部分，以及位于第二部分外侧的第三部分 并且延伸到突片的顶表面以面向与第一和第二部分中的每一个相同的方向。 在平面图中，半导体芯片的外边缘位于突片的第三部分和第二部分之间，并且将半导体芯片固定到突片的粘合剂材料的外边缘位于半导体芯片和第二部分之间 。

公开(公告)号：US20180306844A1

公开(公告)日：2018-10-25

申请号：US16019050

申请日：2018-06-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TAKADA ,  Nobuya KOIKE ,  Akihiro NAKAHARA ,  Makoto TANAKA

IPC: G01R17/16 ,  H01L29/78 ,  H01L23/535 ,  H01L27/02 ,  G01R19/00 ,  H01L29/08 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: G01R17/16 ,  G01R19/0092 ,  H01L21/823487 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0251 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.

公开(公告)号：US20170089957A1

公开(公告)日：2017-03-30

申请号：US15271537

申请日：2016-09-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TAKADA ,  Nobuya KOIKE ,  Akihiro NAKAHARA ,  Makoto TANAKA

IPC: G01R17/16 ,  G01R19/00 ,  H01L29/08 ,  H01L27/088 ,  H01L23/535

CPC classification number: G01R17/16 ,  G01R19/0092 ,  H01L21/823487 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0251 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.

公开(公告)号：US20160133549A1

公开(公告)日：2016-05-12

申请号：US14981452

申请日：2015-12-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TAKADA ,  Tadatoshi DANNO ,  Hirokazu KATO

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.