公开(公告)号：US10109622B2

公开(公告)日：2018-10-23

申请号：US15792009

申请日：2017-10-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi Mihara

IPC: H01L27/108 ,  H01L27/06 ,  G11C16/04 ,  H01L27/11565 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11568

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

公开(公告)号：US09735169B2

公开(公告)日：2017-08-15

申请号：US15384602

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi Mihara

IPC: H01L27/11568 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/7923

Abstract: A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.

公开(公告)号：US09543314B2

公开(公告)日：2017-01-10

申请号：US14828473

申请日：2015-08-17

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi Mihara

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect to the control gate electrode is provided which improves its performance. A control gate electrode which configures a memory cell, and a metallic film which configures part of the memory gate electrode are formed by a so-called gate last process. Thus, the memory gate electrode is configured by a silicon film corresponding to a p-type semiconductor film being in contact with an ONO film, and the metallic film. Further, a contact plug is coupled to both of the silicon film and the metallic film which configure the memory gate electrode.

Abstract translation: 提供一种半导体器件，其包括具有控制栅电极和通过电荷累积层相对于控制栅电极形成的存储栅电极的存储单元，其提高其性能。 构成存储单元的控制栅极电极和配置存储栅电极的一部分的金属膜通过所谓的栅极最后工艺形成。 因此，存储栅电极由对应于与ONO膜接触的p型半导体膜的金属膜和金属膜构成。 此外，接触插塞耦合到构成存储栅电极的硅膜和金属膜两者。

公开(公告)号：US08951869B2

公开(公告)日：2015-02-10

申请号：US14139991

申请日：2013-12-24

Applicant: Renesas Electronics Corporation

Inventor： Keisuke Tsukamoto ,  Tatsuyoshi Mihara

IPC: H01L21/8234 ,  H01L21/8239 ,  H01L21/28 ,  H01L21/285 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/51

CPC classification number: H01L27/11531 ,  H01L21/265 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/324 ,  H01L27/11521 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S438/926

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Abstract translation: 在半导体衬底的存储单元区域中形成非易失性存储器的存储单元的控制栅极电极和存储栅电极，并且在外围电路区域中形成虚拟栅电极。 然后，在存储单元区域中形成用于存储单元的源极或漏极的n +型半导体区域，并且在外围电路区域中形成用于MISFET的源极或漏极的n +型半导体区域。 然后，在n +型半导体区域上形成金属硅化物层，但是在控制栅电极，存储栅电极和栅电极之上不形成金属硅化物层。 随后，去除栅电极并用MISFET的栅电极代替。 然后，在去除栅电极并用MISFET的栅电极代替之后，在存储栅电极和控制栅极上形成金属硅化物层。

公开(公告)号：US20140302646A1

公开(公告)日：2014-10-09

申请号：US14244952

申请日：2014-04-04

Applicant: Renesas Electronics Corporation

Inventor： Yuichi Hirano ,  Tatsuyoshi Mihara ,  Keisuke Tsukamoto

IPC: H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/31053 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/792

Abstract: A performance and reliability of a semiconductor device are improved. On a semiconductor substrate, a gate electrode for a first MISFET and a dummy gate electrode for a second MISFET are formed, and then, an insulating film is partially formed on the gate electrode. Then, on the semiconductor substrate, an insulating film is formed so as to cover the dummy gate electrode, the gate electrode and other insulating film. Then, the dummy gate electrode is exposed by polishing the insulating film. In this polishing, the insulating film is polished under a condition that a polishing speed of the other insulating film is smaller than a polishing speed of the insulating film. Then, after the dummy gate electrode is removed, the gate electrode for the second MISFET is formed in a region where the dummy gate electrode has been removed.

Abstract translation: 提高了半导体器件的性能和可靠性。 在半导体衬底上，形成用于第一MISFET的栅电极和用于第二MISFET的伪栅电极，然后在栅电极上部分地形成绝缘膜。 然后，在半导体基板上形成绝缘膜，以覆盖伪栅电极，栅电极等绝缘膜。 然后，通过抛光绝缘膜来暴露伪栅电极。 在该研磨中，在其他绝缘膜的研磨速度小于绝缘膜的研磨速度的条件下对绝缘膜进行研磨。 然后，在去除虚拟栅电极之后，在去除了虚拟栅电极的区域中形成用于第二MISFET的栅电极。

公开(公告)号：US10559500B2

公开(公告)日：2020-02-11

申请号：US15950688

申请日：2018-04-11

Applicant: Renesas Electronics Corporation

Inventor： Koji Maekawa ,  Tatsuyoshi Mihara

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/06 ,  H01L29/36

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

公开(公告)号：US10325921B2

公开(公告)日：2019-06-18

申请号：US16189373

申请日：2018-11-13

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi Mihara

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L29/792 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575

Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.

公开(公告)号：US10204789B2

公开(公告)日：2019-02-12

申请号：US15404463

申请日：2017-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu Ogata ,  Tatsuyoshi Mihara

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/49 ,  H01L29/51

Abstract: Over a semiconductor substrate, a memory gate electrode for a nonvolatile memory cell is formed via a first insulating film having an internal charge storage portion. A dummy control gate electrode is formed so as to be adjacent to the memory gate electrode via a second insulating film. The memory and the dummy control gate electrodes are made of different materials. A third insulating film is formed so as to cover the memory and the dummy control gate electrodes and then polished to expose the memory and the dummy control gate electrodes. Then, etching is performed under a condition in which the memory gate electrode is less likely to be etched than the dummy control gate electrode to remove the dummy control gate electrode. Then, in a trench as a region from which the dummy control gate electrode is removed, a control gate electrode for the memory cell is formed.

公开(公告)号：US09847328B2

公开(公告)日：2017-12-19

申请号：US15429512

申请日：2017-02-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi Mihara

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/66 ,  H01L27/11568 ,  H01L29/792 ,  H01L27/11565 ,  G11C16/04

CPC classification number: H01L27/0629 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  H01L21/823468 ,  H01L27/1104 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

公开(公告)号：US09831092B2

公开(公告)日：2017-11-28

申请号：US15061870

申请日：2016-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi Mihara

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/1157

CPC classification number: H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344

Abstract: A semiconductor device includes a control gate electrode and a memory gate electrode which are formed over the main surface of a semiconductor substrate in a memory cell region, and a first electrode and a second electrode which are formed over the main surface of the semiconductor substrate in a shunt region. The first electrode is formed integrally with the control gate electrode, and the second electrode is formed integrally with the memory gate electrode. The second electrode includes a first section formed along the side wall of the first electrode, and a second section extending along the main surface of the semiconductor substrate. Also, the height of the upper surface of the first electrode with respect to the main surface of the semiconductor substrate is generally same to the height of the upper surface of the first section of the second electrode.