公开(公告)号：US20220077191A1

公开(公告)日：2022-03-10

申请号：US17528585

申请日：2021-11-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuta TSUCHIYA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/11 ,  H03K17/687 ,  H01L29/06

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

公开(公告)号：US20160155825A1

公开(公告)日：2016-06-02

申请号：US15017459

申请日：2016-02-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiaki IWAMATSU ,  Takashi TERADA ,  Hirofumi SHINOHARA ,  Kozo ISHIKAWA ,  Ryuta TSUCHIYA ,  Kiyoshi HAYASHI

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/308 ,  H01L21/321

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

公开(公告)号：US20130240991A1

公开(公告)日：2013-09-19

申请号：US13784709

申请日：2013-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuta TSUCHIYA ,  Shinichiro KIMURA

IPC: H01L27/12

CPC classification number: H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

Abstract: A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer), in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

Abstract translation: 一种器件及其制造方法，其中器件包括单晶半导体衬底和通过薄的掩埋绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的SOI衬底， 在其中以相同的步骤形成SOI型MISFET和体型MISFET的阱扩散层区域，漏极区域，栅极绝缘膜和栅极电极。 本体型MISFET和SOI型MISFET形成在同一衬底上，从而通过制造SOI型MISFET和体型MISFET的制造步骤，可以减少电路板面积并简化工艺。

公开(公告)号：US20160372486A1

公开(公告)日：2016-12-22

申请号：US15251238

申请日：2016-08-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuta TSUCHIYA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L27/11 ,  H01L21/84 ,  H01L29/06

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

公开(公告)号：US20160156350A1

公开(公告)日：2016-06-02

申请号：US15018533

申请日：2016-02-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuta TSUCHIYA ,  Toshiaki IWAMATSU

IPC: H03K17/687

CPC classification number: H01L27/1203 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H03K17/6872

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.