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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10249638B2

    公开(公告)日：2019-04-02

    申请号：US15904349

    申请日：2018-02-24

    Applicant: Renesas Electronics Corporation

    Inventor： Tomohiro Yamashita ,  Tamotsu Ogata ,  Masamichi Fujito ,  Tomoya Saito

    IPC: H01L27/11568 ,  H01L27/11573 ,  H01L49/02

    Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

    Semiconductor device and semiconductor system
    2.
    发明授权
    Semiconductor device and semiconductor system 有权

    公开(公告)号：US12154610B2

    公开(公告)日：2024-11-26

    申请号：US17847967

    申请日：2022-06-23

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Genta Watanabe ,  Ken Matsubara ,  Tomoya Saito ,  Akihiko Kanda ,  Koichi Takeda ,  Takahiro Shimoi

    IPC: G11C11/08 ,  G11C11/16

    Abstract: A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10559581B2

    公开(公告)日：2020-02-11

    申请号：US16269797

    申请日：2019-02-07

    Applicant: Renesas Electronics Corporation

    Inventor： Tomohiro Yamashita ,  Tamotsu Ogata ,  Masamichi Fujito ,  Tomoya Saito

    IPC: H01L21/28 ,  H01L27/11573 ,  H01L49/02 ,  H01L27/11568 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L27/06 ,  H01L29/78 ,  H01L29/792 ,  H01L29/94 ,  H01L27/1157 ,  H01L29/417

    Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10796768B2

    公开(公告)日：2020-10-06

    申请号：US16352273

    申请日：2019-03-13

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Tomoya Saito ,  Naoki Takizawa

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

    Abstract: It is to optimize the initial threshold voltages of each memory area in a semiconductor memory device including a plurality of memory areas. A semiconductor memory device according to the embodiment includes a first memory area for storing data and a second memory area for storing the information related to the first memory area. In the respective memory cells arranged in the first and the second memory areas, the initial threshold voltages of the memory cells arranged in the second memory area are designed to be higher than those of the memory cells arranged in the first memory area.

    Flash memory
    6.
    发明授权
    Flash memory 有权

    公开(公告)号：US10031792B2

    公开(公告)日：2018-07-24

    申请号：US15650282

    申请日：2017-07-14

    Applicant: Renesas Electronics Corporation

    Inventor： Tomoya Saito ,  Masamichi Fujito ,  Koichi Ando ,  Takashi Hashimoto

    IPC: G11C7/00 ,  G06F11/07

    Abstract: The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10395742B2

    公开(公告)日：2019-08-27

    申请号：US15434346

    申请日：2017-02-16

    Applicant: Renesas Electronics Corporation

    Inventor： Tomoya Saito

    IPC: G11C16/14 ,  H01L27/11568 ,  G11C16/04 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

    Abstract: A memory cell of a split gate type MONOS memory is formed over a plate-shaped fin being a part of a semiconductor substrate. In a data erase operation, in a selected memory cell on which erasing is performed, a drain region is applied with 0 V, a memory gate electrode is applied with a positive voltage, and accordingly, erasing is performed by the FN mechanism. Also, in the data erase operation, in an unselected memory cell on which the erasing is not performed, connected to the same memory gate line as the above-described selected memory cell, the drain region is in an open state, and the memory gate electrode is applied with the positive voltage, whereby an induced voltage region is generated in a channel region. Thus, a potential difference between the channel region and the memory gate electrode is small, and accordingly, the erasing is not performed.

    Semiconductor device, and unique ID generation method
    8.
    发明授权
    Semiconductor device, and unique ID generation method 有权

    公开(公告)号：US10224083B2

    公开(公告)日：2019-03-05

    申请号：US15926672

    申请日：2018-03-20

    Applicant: Renesas Electronics Corporation

    Inventor： Tomoya Saito

    IPC: G11C16/10 ,  G11C16/28 ,  G11C8/12 ,  G11C7/10 ,  G06F12/06 ,  G11C8/06

    Abstract: A semiconductor device according to one embodiment includes a unique ID generation circuit configured to generate a unique ID using a memory array including a plurality of complementary cells, each of the complementary cells includes first and second memory cells MC1 and MC2. The unique ID generation circuit uses, when data in the complementary cell read out in a first state in which an initial threshold voltage of the first memory cell MC1 has been virtually offset and data in the complementary cell read out in a second state in which an initial threshold voltage of the second memory cell MC2 has been virtually offset coincide with each other, the data in the complementary cell as the unique ID.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150349143A1

    公开(公告)日：2015-12-03

    申请号：US14712903

    申请日：2015-05-14

    Applicant: Renesas Electronics Corporation

    Inventor： Masao Inoue ,  Yoshiki Maruyama ,  Tomoya Saito ,  Atsushi Yoshitomi

    IPC: H01L29/792 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423

    CPC classification number: H01L21/28282 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    Abstract: An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film.

    Abstract translation: 在包括存储元件的半导体器件的性能方面实现了改进。 在半导体衬底上，用于存储元件的栅电极经由作为存储元件的栅极绝缘膜的绝缘膜形成。 绝缘膜按照与基板分开的顺序包括第一，第二，第三，第四和第五绝缘膜。 第二绝缘膜具有电荷存储功能。 第一和第三绝缘膜中的每一个的带隙大于第二绝缘膜的带隙。 第四绝缘膜的带隙小于第三绝缘膜的带隙。 第五绝缘膜的带隙小于第四绝缘膜的带隙。

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