公开(公告)号：US11094833B2

公开(公告)日：2021-08-17

申请号：US16452261

申请日：2019-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masao Inoue ,  Masaru Kadoshima ,  Yoshiyuki Kawashima ,  Ichiro Yamakawa

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

Abstract: A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen.

公开(公告)号：US08823110B2

公开(公告)日：2014-09-02

申请号：US13945282

申请日：2013-07-18

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Shimamoto ,  Jiro Yugami ,  Masao Inoue ,  Masaharu Mizutani

IPC: H01L29/76 ,  H01L21/28 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.

Abstract translation: 公开了一种包括n沟道型的第一MISFET和ap沟道型的第二MISFET的半导体器件，每个MISFET被配置有具有硅氧化膜或氮氧化硅膜的栅极绝缘膜和包括 位于栅极绝缘膜上的导电硅膜。 金属元素如Hf在第一和第二MISFET中的栅电极和栅极绝缘膜之间的界面附近引入，使得表面密度为1×1013至5×1014原子/ cm2的金属原子包含在界面附近 并且第一和第二MISFET中的每一个具有含有浓度等于或低于1.2×1018 / cm3的杂质的沟道区。

公开(公告)号：US11081596B2

公开(公告)日：2021-08-03

申请号：US15904601

申请日：2018-02-26

Applicant: Renesas Electronics Corporation

Inventor： Masaru Kadoshima ,  Masao Inoue

IPC: H01L29/792 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11568 ,  H01L21/02 ,  H01L29/51

Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.

公开(公告)号：US20180308964A1

公开(公告)日：2018-10-25

申请号：US16019047

申请日：2018-06-26

Applicant: Renesas Electronics Corporation

Inventor： Masaru Kadoshima ,  Masao Inoue

IPC: H01L29/739 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L29/7397 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/1095

Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating.In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.

公开(公告)号：US20150340479A1

公开(公告)日：2015-11-26

申请号：US14712894

申请日：2015-05-14

Applicant: Renesas Electronics Corporation

Inventor： Masaru Kadoshima ,  Masao Inoue

IPC: H01L29/739 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/1095

Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating.In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.

Abstract translation: 本发明在半导体器件的制造工艺中可以抑制：杂质从衬底扩散到半导体层; 并且晶体管的耐压降低。 在本发明中，在第一导电型基底上形成第一导电型外延层。 外延层的杂质浓度低于基底的杂质浓度。 第二导电型第一嵌入层和第二导电型第二嵌入层形成在外延层中。 第二嵌入层比第一嵌入层更深，远离第一嵌入层，杂质浓度低于第一嵌入层。 晶体管进一步形成在外延层中。

公开(公告)号：US20150060991A1

公开(公告)日：2015-03-05

申请号：US14470719

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Masaharu Mizutani ,  Masao Inoue ,  Hiroshi Umeda ,  Masaru Kadoshima

IPC: H01L29/792 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/02148 ,  H01L21/02178 ,  H01L21/02318 ,  H01L21/02359 ,  H01L21/28229 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66833

Abstract: The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.

Abstract translation: 提高了具有存储元件的半导体器件的性能。 作为用于存储元件的栅极绝缘膜的绝缘膜形成在半导体衬底上，并且在绝缘膜上形成用于存储元件的栅电极。 绝缘膜具有第一绝缘膜，第二绝缘膜及其上的第三绝缘膜。 第二绝缘膜是具有电荷累积功能并含有铪，硅和氧的高介电常数绝缘膜。 第一绝缘膜和第三绝缘膜中的每一个具有比第二绝缘膜的带隙大的带隙。

公开(公告)号：US12206008B2

公开(公告)日：2025-01-21

申请号：US17513404

申请日：2021-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima ,  Masao Inoue

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/792

Abstract: A memory cell which is a non-volatile memory cell includes a gate insulating film having a charge storage layer capable of retaining charge and a memory gate electrode formed on the gate insulating film. The charge storage layer includes a first insulating film containing hafnium and silicon and a second insulating film formed on the first insulating film and containing hafnium and silicon. Here, a hafnium concentration of the first insulating film is lower than a hafnium concentration of the second insulating film, and a bandgap of the first insulating film is larger than a bandgap of the second insulating film.

公开(公告)号：US10672916B2

公开(公告)日：2020-06-02

申请号：US16126784

申请日：2018-09-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masao Inoue

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.

公开(公告)号：US10217872B2

公开(公告)日：2019-02-26

申请号：US15626092

申请日：2017-06-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Masao Inoue ,  Atsushi Yoshitomi

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.

公开(公告)号：US11133422B2

公开(公告)日：2021-09-28

申请号：US16857986

申请日：2020-04-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masao Inoue

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.