公开(公告)号：US20180301463A1

公开(公告)日：2018-10-18

申请号：US16012362

申请日：2018-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11563 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40117

Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US20180047742A1

公开(公告)日：2018-02-15

申请号：US15672909

申请日：2017-08-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11563

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573

Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US20190363095A1

公开(公告)日：2019-11-28

申请号：US16404095

申请日：2019-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto OMIZU ,  Takashi HASHIMOTO ,  Hideaki YAMAKOSHI

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L21/762 ,  H01L21/28 ,  H01L21/3065

Abstract: The manufacturing method of the semiconductor device includes a step of forming the gate dielectric film GI2 and the polysilicon layer PS2 on the main surface SUBa of the semiconductor substrate SUB, a step of forming the isolation trench TR in the semiconductor substrate SUB through the polysilicon layer PS2 and the gate dielectric film GI2, a step of filling the isolation trench TR with the dielectric film, and then a step of polishing the dielectric film to form the element isolation film STI in the isolation trench TR. Further, a method for manufacturing a semiconductor device comprises etching the element isolation film STI to retract the upper surface STIa of the element isolation film STI, then further depositing a polysilicon layer on the polysilicon layer PS2 to form a gate electrode using an anisotropic dry etching method.

公开(公告)号：US20180286881A1

公开(公告)日：2018-10-04

申请号：US15871818

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11568 ,  H01L27/11573 ,  G11C11/40

Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

公开(公告)号：US20230299194A1

公开(公告)日：2023-09-21

申请号：US18061673

申请日：2022-12-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto OMIZU ,  Yuya ABIKO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L21/225 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/407 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/66734

Abstract: Disclosed is a technique for improving performance of a semiconductor device having a trench gate type power MOSFET. Concretely, a method of manufacturing a semiconductor device having a trench gate type power MOSFET comprising: forming a trench in a semiconductor substrate; introducing both of a p-type impurity(Boron) and carbon (C) into a bottom surface of the trench to form a p-type impurity introduced region; forming a gate electrode to fill the trench; forming a channel forming region and a source region at the side of the trench in which the gate electrode is filled; and subjecting a heat treatment to the p-type impurity introduced region to form an electric field relaxation layer having suppressed crystal defects and a controlled shape.

公开(公告)号：US20220123000A1

公开(公告)日：2022-04-21

申请号：US17500297

申请日：2021-10-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto OMIZU

IPC: H01L27/11524 ,  H01L27/12 ,  H01L27/1157

Abstract: A first insulating film is formed on a semiconductor substrate in each of a first region in which a memory transistor is to be formed, a second region in which a selection transistor is to be formed, a third region in which a high-withstand-voltage transistor is to be formed, and a fourth region in which a low-withstand-voltage transistor is to be formed. Subsequently, the first insulating film in each of the first and second regions is removed. A second insulating film is formed on the semiconductor substrate in each of the first and second regions. A third insulating film having a trap level is formed on the second insulating film. The third insulating film in the second region and the second insulating film in the second region are removed. A fourth insulating film is formed on the third insulating film and on the semiconductor substrate in the second region.

公开(公告)号：US20250015147A1

公开(公告)日：2025-01-09

申请号：US18762960

申请日：2024-07-03

Applicant: Renesas Electronics Corporation

Inventor： Yuto OMIZU ,  Yu NAGAHAMA

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The insulating film IF1 is retracted so that the position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. An embedded insulating film EF1 is formed to cover the field plate electrode FP and the insulating film IF1. The embedded insulating film EF1 is retracted so that the position of the upper surface of the embedded insulating film EF1 is lower than the position of the upper surface of the field plate electrode FP. A gate insulating film GI is formed inside the trench TR, and an insulating film IF2 is formed to cover the field plate electrode FP. A gate electrode is formed on the field plate electrode FP via the insulating film IF2.

公开(公告)号：US20190279998A1

公开(公告)日：2019-09-12

申请号：US16278951

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Shinichiro ABE ,  Takashi HASHIMOTO ,  Yuto OMIZU

IPC: H01L27/11573 ,  H01L27/12 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/792 ,  H01L27/02

Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.