公开(公告)号：US20180047742A1

公开(公告)日：2018-02-15

申请号：US15672909

申请日：2017-08-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11563

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573

Abstract: An improvement is achieved in the reliability of a semiconductor device. A structure is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate located in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate located in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate located in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.

公开(公告)号：US20210013328A1

公开(公告)日：2021-01-14

申请号：US17031975

申请日：2020-09-25

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro ABE

IPC: H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  H01L27/11573

Abstract: An insulating film configuring an uppermost layer of a gate insulating film of a memory cell comprises a silicon oxide film and is a layer to which a metal or metal oxide is added. A formation step of the insulating film comprises the steps of: forming the silicon oxide film; and adding the metal or the metal oxide in an atomic or molecular state by a sputtering process onto the silicon oxide film. Oxide of the metal has a higher dielectric constant than silicon oxide, and the metal oxide has a higher dielectric constant than silicon oxide. A High-K added layer is thus used as the insulating film configuring the gate insulating film of the memory cell, thereby a high saturation level of a threshold voltage can be maintained while a drive voltage (applied voltage for erase or write) is reduced, leading to improvement in reliability of the memory cell.

公开(公告)号：US20190279998A1

公开(公告)日：2019-09-12

申请号：US16278951

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Shinichiro ABE ,  Takashi HASHIMOTO ,  Yuto OMIZU

IPC: H01L27/11573 ,  H01L27/12 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/792 ,  H01L27/02

Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.

公开(公告)号：US20180308957A1

公开(公告)日：2018-10-25

申请号：US15898201

申请日：2018-02-15

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro ABE

IPC: H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L27/115 ,  G11C16/04

CPC classification number: H01L29/66833 ,  G11C16/0475 ,  H01L21/28194 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

Abstract: An insulating film configuring an uppermost layer of a gate insulating film of a memory cell comprises a silicon oxide film and is a layer to which a metal or metal oxide is added. A formation step of the insulating film comprises the steps of: forming the silicon oxide film; and adding the metal or the metal oxide in an atomic or molecular state by a sputtering process onto the silicon oxide film. Oxide of the metal has a higher dielectric constant than silicon oxide, and the metal oxide has a higher dielectric constant than silicon oxide. A High-K added layer is thus used as the insulating film configuring the gate insulating film of the memory cell, thereby a high saturation level of a threshold voltage can be maintained while a drive voltage (applied voltage for erase or write) is reduced, leading to improvement in reliability of the memory cell.

公开(公告)号：US20160093499A1

公开(公告)日：2016-03-31

申请号：US14869988

申请日：2015-09-29

Applicant: Renesas Electronics Corporation

Inventor： Kazuharu YAMABE ,  Shinichiro ABE ,  Shoji YOSHIDA ,  Hideaki YAMAKOSHI ,  Toshio KUDO ,  Seiji MURANAKA ,  Fukuo OWADA ,  Daisuke OKADA

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L21/28194 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.

Abstract translation: 提供具有改进性能的半导体器件，同时提高半导体器件的制造步骤中的吞吐量。 在半导体衬底上形成由第一，第二，第三，第四和第五绝缘膜构成的绝缘膜部分。 第二绝缘膜是第一电荷存储膜，第四绝缘膜是第二电荷存储膜。 第一电荷储存膜含有硅和氮; 第三绝缘膜含有硅和氧; 并且第二电荷储存膜含有硅和氮。 第三绝缘膜的厚度小于第一电荷存储膜的厚度，并且第二电荷存储膜的厚度大于第一电荷存储膜的厚度。 第三绝缘膜通过用含水处理液处理第一电荷存储膜的上表面而形成。

公开(公告)号：US20190244968A1

公开(公告)日：2019-08-08

申请号：US16243809

申请日：2019-01-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichiro ABE

IPC: H01L27/11573 ,  H01L27/11568

CPC classification number: H01L27/11573 ,  H01L27/11568

Abstract: Reliability of a semiconductor device is improved. A resist pattern having an opening in a first region where a memory transistor is formed and covering other regions is prepared. Next, by ion implantation using this resist pattern as a mask, a channel region is formed in a surface of a semiconductor substrate in the first region, and a nitrogen-introduction portion is formed inside the channel region. Next, the resist pattern is removed. Then, a gate insulating film having a charge storage layer is formed on the semiconductor substrate in the first region, and a gate electrode is formed on the gate insulating film.

公开(公告)号：US20180286881A1

公开(公告)日：2018-10-04

申请号：US15871818

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11568 ,  H01L27/11573 ,  G11C11/40

Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.

公开(公告)号：US20170278854A1

公开(公告)日：2017-09-28

申请号：US15468673

申请日：2017-03-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichiro ABE ,  Masaaki SHINOHARA

IPC: H01L27/1157 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.

公开(公告)号：US20180366556A1

公开(公告)日：2018-12-20

申请号：US15957785

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichiro ABE ,  Takashi Hashimoto ,  Hideaki Yamakoshi ,  Yuto Omizu

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L21/8239

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

公开(公告)号：US20180301463A1

公开(公告)日：2018-10-18

申请号：US16012362

申请日：2018-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki YAMAKOSHI ,  Takashi HASHIMOTO ,  Shinichiro ABE ,  Yuto OMIZU

IPC: H01L27/11563 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40117

Abstract: A semiconductor device is obtained in which a first insulating film for a gate insulating film of a memory element is formed over a semiconductor substrate in a memory region, a second insulating film for a gate insulating film of a lower-breakdown-voltage MISFET is formed over the semiconductor substrate in a lower-breakdown-voltage MISFET formation region, and a third insulating film for a gate insulating film of a higher-breakdown-voltage MISFET is formed over the semiconductor substrate in a higher-breakdown-voltage MISFET formation region. Subsequently, a film for gate electrodes is formed and then patterned to form the respective gate electrodes of the memory element, the lower-breakdown-voltage MISFET, and the higher-breakdown-voltage MISFET. The step of forming the second insulating film is performed after the step of forming the first insulating film. The step of forming the third insulating film is performed before the step of forming the first insulating film.