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公开(公告)号：US10833145B2
公开(公告)日：2020-11-10
申请号：US16250453
申请日：2019-01-17
Applicant: ROHM CO., LTD.
Inventor： Hiroshi Tamagawa , Yasuhiro Kondo , Yasuhiro Fuwa , Hiroyuki Okada , Eiji Nukaga , Katsuya Matsuura
IPC: H01C1/14 , H01C13/02 , H01L49/02 , H01L27/08 , H01L21/308 , H01L27/06 , H01L21/3065 , H01C17/242 , H01C17/00 , H05K3/34
Abstract: A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.
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公开(公告)号：US10304633B2
公开(公告)日：2019-05-28
申请号：US15836208
申请日：2017-12-08
Applicant: ROHM CO., LTD.
Inventor： Hiroyuki Okada , Yasuhiro Fuwa
Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.
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3.发明申请公开(公告)号：US20140225220A1
公开(公告)日：2014-08-14
申请号：US14348581
申请日：2012-09-28
Applicant: ROHM CO., LTD.
Inventor： Hiroshi Tamagawa , Yasuhiro Kondo , Yasuhiro Fuwa , Hiroyuki Okada , Eiji Nukaga , Katsuya Matsuura
IPC: H01L27/06
CPC classification number: H01L28/20 , H01C1/14 , H01C13/02 , H01C17/006 , H01C17/242 , H01L21/3065 , H01L21/3083 , H01L27/0676 , H01L27/0802 , H05K3/3431 , H05K2201/10674
Abstract: [Theme] A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired.[Solution Means] A chip resistor 10 is arranged to have a resistor network 14 on a substrate. The resistor network 14 includes a plurality of resistor bodies R arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies R being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films C and fuse films F. By selectively fusing a fuse film F, a resistance unit can be electrically incorporated into the resistor network 14 or electrically separated from the resistor network to make the resistance value of the resistor network 14 the required resistance value.
Abstract translation: [主题]希望具有相同设计结构容易地容纳多种类型的所需电阻值的紧凑且精细的芯片电阻器。 [解决方案]芯片电阻器10布置成在基板上具有电阻网络14。 电阻网络14包括排列成矩阵并具有相等电阻值的多个电阻体R。 多个电阻单元分别由电连接的一个或多个电阻体R布置。 多种类型的电阻单元使用连接导体膜C和熔丝膜F以预定模式连接。通过选择性地熔化熔丝F，电阻单元可以电连接到电阻器网络14中或与电阻器网络电分离 使电阻网络14的电阻值成为所需电阻值。
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公开(公告)号：US10777360B2
公开(公告)日：2020-09-15
申请号：US16385876
申请日：2019-04-16
Applicant: ROHM CO., LTD.
Inventor： Hiroyuki Okada , Yasuhiro Fuwa
Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.
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公开(公告)号：US09859061B2
公开(公告)日：2018-01-02
申请号：US14372741
申请日：2012-12-26
Applicant: ROHM CO., LTD.
Inventor： Hiroyuki Okada , Yasuhiro Fuwa
CPC classification number: H01G5/011 , H01G4/015 , H01G4/33 , H01G4/385 , H01G4/40 , H01G5/38 , H01L27/016 , H01L28/40
Abstract: [Theme] To provide a chip capacitor capable of easily and rapidly accommodating a plurality of types of capacitance values using a common design and a method for manufacturing the chip capacitor. [Solution] A chip capacitor 1 includes a substrate 2, a first external electrode 3, a second external electrode 4, capacitor elements C1 to C19, and fuses F1 to F9 disposed on the substrate 2. The capacitor elements C1 to C19 respectively include a first electrode film 11, a first capacitance film 12 on the first electrode film 11, a second electrode film 13 disposed on the first capacitance film 12 and facing the first electrode film 11, a second capacitance film 17 on the second electrode film 13, and a third electrode film 16 disposed on the second capacitance film 17 and facing the second electrode film 13 and are connected between the first external electrode 3 and the second external electrode 4. The fuses F1 to F9 are each interposed between the capacitor elements C1 to C19 and the first external electrode 3 or the second external electrode 4 and are capable of disconnecting each of the capacitor elements C1 to C19.
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Patent Agency Ranking
公开(公告)号：US10403420B2
公开(公告)日：2019-09-03
申请号：US15485640
申请日：2017-04-12
Applicant: ROHM CO., LTD.
Inventor： Hiroyuki Okada , Yasuhiro Kondo
Abstract: A chip resistor including, a substrate having a main surface, a first resistance circuit formed at the main surface of the substrate, a second resistance circuit formed at the main surface of the substrate apart from the first resistance circuit, a common internal electrode formed at the main surface of the substrate and electrically connected to the first resistance circuit and the second resistance circuit, a first internal electrode formed at the main surface of the substrate and electrically connected to the first resistance circuit, a second internal electrode formed at the main surface of the substrate and electrically connected to the second resistance circuit, and a dummy resistance circuit formed in a region between the first resistance circuit and the second resistance circuit at the main surface of the substrate so as to be in an electrically floating state.
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公开(公告)号：US20150022938A1
公开(公告)日：2015-01-22
申请号：US14372741
申请日：2012-12-26
Applicant: ROHM CO., LTD.
Inventor： Hiroyuki Okada , Yasuhiro Fuwa
CPC classification number: H01G5/011 , H01G4/015 , H01G4/33 , H01G4/385 , H01G4/40 , H01G5/38 , H01L27/016 , H01L28/40
Abstract: [Theme] To provide a chip capacitor capable of easily and rapidly accommodating a plurality of types of capacitance values using a common design and a method for manufacturing the chip capacitor. [Solution] A chip capacitor 1 includes a substrate 2, a first external electrode 3, a second external electrode 4, capacitor elements C1 to C19, and fuses F1 to F9 disposed on the substrate 2. The capacitor elements C1 to C19 respectively include a first electrode film 11, a first capacitance film 12 on the first electrode film 11, a second electrode film 13 disposed on the first capacitance film 12 and facing the first electrode film 11, a second capacitance film 17 on the second electrode film 13, and a third electrode film 16 disposed on the second capacitance film 17 and facing the second electrode film 13 and are connected between the first external electrode 3 and the second external electrode 4. The fuses F1 to F9 are each interposed between the capacitor elements C1 to C19 and the first external electrode 3 or the second external electrode 4 and are capable of disconnecting each of the capacitor elements C1 to C19.
Abstract translation: [主题]提供一种能够容易且快速地容纳多种类型的电容值的芯片电容器，其使用共同的设计和制造芯片电容器的方法。 [解决方案]芯片电容器1包括基板2，第一外部电极3，第二外部电极4，电容器元件C1至C19以及设置在基板2上的熔丝F1至F9。电容器元件C1至C19分别包括 第一电极膜11，第一电极膜11上的第一电容膜12，配置在第一电容膜12上并与第一电极膜11相对的第二电极膜13，第二电极膜13上的第二电容膜17， 设置在第二电容膜17上并与第二电极膜13相对并连接在第一外部电极3和第二外部电极4之间的第三电极膜16.保险丝F1至F9分别插入在电容器元件C1至C19之间 和第一外部电极3或第二外部电极4，并且能够断开每个电容器元件C1至C19。
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公开(公告)号：US10224391B2
公开(公告)日：2019-03-05
申请号：US15647592
申请日：2017-07-12
Applicant: ROHM CO., LTD.
Inventor： Hiroshi Tamagawa , Yasuhiro Kondo , Yasuhiro Fuwa , Hiroyuki Okada , Eiji Nukaga , Katsuya Matsuura
IPC: H01L49/02 , H01L27/08 , H01L27/06 , H01L21/308 , H01C1/14 , H01C13/02 , H01L21/3065 , H01C17/242 , H01C17/00 , H05K3/34
Abstract: A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.
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公开(公告)号：US10200007B2
公开(公告)日：2019-02-05
申请号：US15212221
申请日：2016-07-16
Applicant: ROHM CO., LTD.
Inventor： Keisuke Fukae , Yasuhiro Kondo , Katsuya Matsuura , Hiroyuki Okada , Junya Yamagami
Abstract: A filter chip includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a resistor forming region where a resistor is formed. The resistor forming region includes a resistive conductive film formed on the substrate with one end and the other end thereof electrically connected to different ones of the external terminals, and a fuse portion integrally formed with the resistive conductive film. The fuse portion is cuttably provided to electrically connect a part of the resistive conductive film to the external terminals, or to electrically separate a part of the resistive conductive film from the external terminals.
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公开(公告)号：US09735225B2
公开(公告)日：2017-08-15
申请号：US14956939
申请日：2015-12-02
Applicant: ROHM CO., LTD.
Inventor： Hiroshi Tamagawa , Yasuhiro Kondo , Yasuhiro Fuwa , Hiroyuki Okada , Eiji Nukaga , Katsuya Matsuura
IPC: H01C10/00 , H01L49/02 , H01L27/08 , H01L27/06 , H01L21/308 , H01C1/14 , H01C13/02 , H01L21/3065 , H01C17/242 , H01C17/00 , H05K3/34
CPC classification number: H01L28/20 , H01C1/14 , H01C13/02 , H01C17/006 , H01C17/242 , H01L21/3065 , H01L21/3083 , H01L27/0676 , H01L27/0802 , H05K3/3431 , H05K2201/10674
Abstract: A compact and refined chip resistor, with which a plurality of types of required resistance values can be accommodated readily with the same design structure, was desired. The chip resistor is arranged to have a resistor network on a substrate. The resistor network includes a plurality of resistor bodies arrayed in a matrix and having an equal resistance value. A plurality of types of resistance units are respectively arranged by one or a plurality of the resistor bodies being connected electrically. The plurality of types of resistance units are connected in a predetermined mode using connection conductor films and fuse films. By selectively fusing a fuse film, a resistance unit can be electrically incorporated into the resistor network or electrically separated from the resistor network to make the resistance value of the resistor network the required resistance value.
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