公开(公告)号：US20060190744A1

公开(公告)日：2006-08-24

申请号：US10906476

申请日：2005-02-22

申请人： Rafael Blanco ,  John Cohn ,  Kenneth Goodnow ,  Douglas Stout ,  Sebastian Ventrone

发明人： Rafael Blanco ,  John Cohn ,  Kenneth Goodnow ,  Douglas Stout ,  Sebastian Ventrone

IPC分类号： G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/26 ,  G06F1/3203 ,  Y02D10/171

摘要： An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage island) to be switched on to or off the power grid.

摘要翻译： 集成电路具有电网和一组可独立切换的电压岛，以及用于测量电网电压和历史的系统和方法，以确定允许大容性负载（例如， 电压岛）被接通或断开电网。

公开(公告)号：US20050041448A1

公开(公告)日：2005-02-24

申请号：US10604328

申请日：2003-07-11

申请人： Rafael Blanco ,  John Cohn ,  Kenneth Goodnow ,  Douglas Stout ,  Sebastian Ventrone

发明人： Rafael Blanco ,  John Cohn ,  Kenneth Goodnow ,  Douglas Stout ,  Sebastian Ventrone

IPC分类号： G11C19/08 ,  H01L20060101

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

摘要翻译： 一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

公开(公告)号：US20060090149A1

公开(公告)日：2006-04-27

申请号：US10904056

申请日：2004-10-21

申请人： Rafael Blanco ,  Suzanne Granato ,  Francis Kampf ,  Douglas Massey

发明人： Rafael Blanco ,  Suzanne Granato ,  Francis Kampf ,  Douglas Massey

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.

摘要翻译： 一种用于测试电路设计的方法和系统。 该方法包括生成电路设计的仿真模型，电路设计包括一个或多个源锁存器，一个或多个目标锁存器和连接在源锁存器和目的地锁存器之间的逻辑功能; 通过在每个源锁存器的输出和逻辑功能的输入之间插入随机偏差仅在模拟模型的源锁存器和目标锁存器之间的异步数据路径中来产生模拟模型的修改的仿真模型; 并运行修改后的仿真模型。

公开(公告)号：US07107469B2

公开(公告)日：2006-09-12

申请号：US10604328

申请日：2003-07-11

申请人： Rafael Blanco ,  John M. Cohn ,  Kenneth J. Goodnow ,  Douglas W. Stout ,  Sebastian T. Ventrone

发明人： Rafael Blanco ,  John M. Cohn ,  Kenneth J. Goodnow ,  Douglas W. Stout ,  Sebastian T. Ventrone

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

摘要翻译： 一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

公开(公告)号：US07222248B2

公开(公告)日：2007-05-22

申请号：US10906476

申请日：2005-02-22

申请人： Rafael Blanco ,  John M. Cohn ,  Kenneth J. Goodnow ,  Douglas W. Stout ,  Sebastian T. Ventrone

发明人： Rafael Blanco ,  John M. Cohn ,  Kenneth J. Goodnow ,  Douglas W. Stout ,  Sebastian T. Ventrone

IPC分类号： G06F1/26 ,  G06F11/30

CPC分类号： G06F1/3287 ,  G06F1/26 ,  G06F1/3203 ,  Y02D10/171

摘要： An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage island) to be switched on to or off the power grid.

摘要翻译： 集成电路具有电网和一组可独立切换的电压岛，以及用于测量电网电压和历史的系统和方法，以确定允许大容性负载（例如， 电压岛）被接通或断开电网。

公开(公告)号：US06720673B2

公开(公告)日：2004-04-13

申请号：US09832520

申请日：2001-04-11

申请人： Rafael Blanco ,  Sebastian T. Ventrone

发明人： Rafael Blanco ,  Sebastian T. Ventrone

IPC分类号： H02J900

CPC分类号： H02J3/38 ,  H02J2003/388 ,  Y10T307/305 ,  Y10T307/391 ,  Y10T307/615

摘要： A circuit for fencing input signals to circuits in a voltage island when switching between a normal and a standby power supply is disclosed. A voltage detector detects the switch over in power source and generates a power switch signal. The power switch signal is synchronized to a standby clock and a normal clock. The synchronized standby clock signal is delayed by a counter to allow circuit stabilization. The normal and standby clock signals are logically combined and used to fence input signals to the circuits on the voltage islands.

摘要翻译： 公开了一种用于在正常和备用电源之间切换时将输入信号屏蔽到电压岛中的电路的电路。 电压检测器检测电源中的开关并产生电源开关信号。 电源开关信号与待机时钟和正常时钟同步。 同步待机时钟信号被延迟一个计数器，以允许电路稳定。 正常和待机时钟信号被逻辑组合，用于将输入信号围绕在电压岛上的电路上。

公开(公告)号：US5568075A

公开(公告)日：1996-10-22

申请号：US453587

申请日：1995-05-30

申请人： Brian W. Curran ,  Rafael Blanco

发明人： Brian W. Curran ,  Rafael Blanco

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03K5/13

CPC分类号： G11C7/22 ,  G11C7/1072 ,  H03K5/131 ,  H03K5/133

摘要： A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

公开(公告)号：US07406579B2

公开(公告)日：2008-07-29

申请号：US11160184

申请日：2005-08-19

申请人： Rafael Blanco ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Rafael Blanco ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G06F12/00

CPC分类号： G06F12/0886 ,  G06F12/0864

摘要： The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory. The selected line width is used in communicating with one or more processors. This provides increased flexibility and efficiency for communicating with the memory. In particular, a register can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache, multiple ways of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task, a processor, and/or a performance evaluation.

摘要翻译： 本发明提供了选择性地改变存储器的线宽，即选择存储器的多条线宽之一。 选择的线宽用于与一个或多个处理器进行通信。 这提高了与内存通信的灵活性和效率。 特别地，可以基于期望的线宽来设置寄存器，并且随后在将数据定位在存储器中时使用。 所选线宽可以与存储器中的每个数据块相关联，以允许同时使用多个线宽。 当在缓存中实现时，高速缓存的多种方式可以被处理为一组以在单个存储器操作期间提供数据。 线宽可以根据任务，处理器和/或性能评估而变化。

公开(公告)号：US07251794B2

公开(公告)日：2007-07-31

申请号：US10904056

申请日：2004-10-21

申请人： Rafael Blanco ,  Suzanne Granato ,  Francis A. Kampf ,  Douglas T. Massey

发明人： Rafael Blanco ,  Suzanne Granato ,  Francis A. Kampf ,  Douglas T. Massey

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.

摘要翻译： 一种用于测试电路设计的方法和系统。 该方法包括生成电路设计的仿真模型，电路设计包括一个或多个源锁存器，一个或多个目标锁存器和连接在源锁存器和目的地锁存器之间的逻辑功能; 通过在每个源锁存器的输出和逻辑功能的输入之间插入随机偏差仅在模拟模型的源锁存器和目标锁存器之间的异步数据路径中来产生模拟模型的修改的仿真模型; 并运行修改后的仿真模型。

公开(公告)号：US5554946A

公开(公告)日：1996-09-10

申请号：US224927

申请日：1994-04-08

申请人： Brian W. Curran ,  Rafael Blanco

发明人： Brian W. Curran ,  Rafael Blanco

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03K5/13

CPC分类号： G11C7/22 ,  G11C7/1072 ,  H03K5/131 ,  H03K5/133

摘要： A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

摘要翻译： 可编程的定时信号发生器沿着包括串联连接的反相器的延迟链传播数字波，其具有足够的级，使得在一个系统时钟周期期间波的边缘将不会传播到结束。 每个时钟周期对延迟链进行采样，并对波进行的点进行编码。 可编程，精细的前沿和精细的后沿寄存器作为时钟周期时间的一小部分存储定时信号前沿和后沿相对于时钟边沿的期望位置。