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    Method for forming a conductive structure having a composite or amorphous barrier layer
    1.
    发明授权
    Method for forming a conductive structure having a composite or amorphous barrier layer 失效
    用于形成具有复合或无定形阻挡层的导电结构的方法

    公开(公告)号：US06136682A

    公开(公告)日：2000-10-24

    申请号：US954149

    申请日：1997-10-20

    申请人： Rama I. Hegde ,  Dean J. Denning ,  Jeffrey L. Klein ,  Philip J. Tobin

    发明人： Rama I. Hegde ,  Dean J. Denning ,  Jeffrey L. Klein ,  Philip J. Tobin

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/4763

    CPC分类号： H01L21/76876 ,  H01L21/76807 ,  H01L21/76843 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002

    摘要： A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.

    摘要翻译： A形成改进的铜阻挡层的方法是通过提供含硅层（10）开始的。 然后使用物理气相沉积工艺来形成薄的氮化钽非晶层（12）。 然后在非晶氮化钽层上沉积薄的无定形氮化钛层（14）。 氮化钽和氮化钛层12和14的总体厚度大致为400埃或更小。 然后将铜材料16沉积在非晶氮化钛的顶部上，其中复合氮化钽层12和氮化钛层14有效地防止铜从层16扩散到层10。

    Semiconductor device having an improved metal interconnect structure
    2.
    发明授权
    Semiconductor device having an improved metal interconnect structure 失效
    具有改进的金属互连结构的半导体器件

    公开(公告)号：US5442235A

    公开(公告)日：1995-08-15

    申请号：US172320

    申请日：1993-12-23

    申请人： Louis C. Parrillo ,  Jeffrey L. Klein

    发明人： Louis C. Parrillo ,  Jeffrey L. Klein

    IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L29/460

    CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L23/53219 ,  H01L2924/0002 ,  Y10S438/927

    摘要： A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).

    摘要翻译： 金属互连结构包括位于耐火金属通孔塞（28）和第一和第二金属互连层（16,32）之间的铜界面层（24,30）。 铜界面层（24,30）被限制在覆盖在第一互连层（16）上并包含通孔塞（28）的绝缘层（20）中的通路孔（22）的区域中。 对界面层（24,30）进行退火处理，以在与界面层（24,30）相邻的互连层（16,32）中提供铜储存器（36,37）。 当电流通过互连结构时，铜储存器（36,37）连续补充从界面耗尽的铜。 一种方法包括将铜选择性沉积在第一金属互连层（16）的暴露区域（23）上，并在上部通孔塞（28）上，然后在形成气体中进行退火以形成铜储存器 36,37）。

    Method for forming self-aligned vias in multi-level metal integrated circuits
    3.
    发明授权
    Method for forming self-aligned vias in multi-level metal integrated circuits 失效
    在多级金属集成电路中形成自对准通孔的方法

    公开(公告)号：US4917759A

    公开(公告)日：1990-04-17

    申请号：US339451

    申请日：1989-04-17

    申请人： Duncan M. Fisher ,  Jeffrey L. Klein

    发明人： Duncan M. Fisher ,  Jeffrey L. Klein

    IPC分类号： H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002

    摘要： A process for forming a via in a semiconductor device using a self-aligned metal pillar to connect metal layers separated by a dielectric. A first aluminum layer is formed on an oxide layer overlying a semiconductor substrate, and a thin tungsten layer is formed and patterned overlying the first aluminum layer. The pattern in this tungsten layer will determine the pattern for the first level of metal interconnect to be formed later in the first aluminum layer. The tungsten layer is etched using the underlying first aluminum layer as an etch stop. A second aluminum layer is then formed overlying the patterned tungsten layer and the exposed regions of the first aluminum layer. In one continuous etching step the second aluminum layer is patterned and etched to form a pillar, and the first aluminum layer is etched to form the first level of metal interconnect in the semiconductor device using the pattern formed earlier in the tungsten layer and to expose regions of the oxide layer. A dielectric is deposited overlying the exposed regions of the oxide layer, the formed pillar, and the thin tungsten layer. This dielectric is etched back to expose the top of the pillar, and then a third aluminum layer is deposited overlying the dielectric to make electrical contact to the exposed surface of the pillar.

    摘要翻译： 在半导体器件中使用自对准金属柱形成通孔以连接由电介质隔开的金属层的工艺。 在覆盖半导体衬底的氧化物层上形成第一铝层，并且形成覆盖在第一铝层上的薄钨层。 该钨层中的图案将确定在第一铝层中稍后形成的第一级金属互连的图案。 使用下面的第一铝层作为蚀刻停止层来蚀刻钨层。 然后形成第二铝层，覆盖图案化的钨层和第一铝层的暴露区域。 在一个连续蚀刻步骤中，对第二铝层进行图案化和蚀刻以形成柱，并且使用在钨层中较早形成的图案，在半导体器件中蚀刻第一铝层以形成第一级金属互连，并暴露区域 的氧化物层。 沉积在氧化物层，形成的柱和薄钨层的暴露区域上的电介质。 将该电介质回蚀以暴露柱的顶部，然后沉积覆盖在电介质上的第三铝层以与柱的暴露表面电接触。

    Method for chemical mechanical polishing a semiconductor device using slurry
    4.
    发明授权
    Method for chemical mechanical polishing a semiconductor device using slurry 失效
    使用浆料对半导体器件进行化学机械抛光的方法

    公开(公告)号：US6027997A

    公开(公告)日：2000-02-22

    申请号：US205423

    申请日：1994-03-04

    申请人： Chris C. Yu ,  Jeffrey F. Hanson ,  Jeffrey L. Klein

    发明人： Chris C. Yu ,  Jeffrey F. Hanson ,  Jeffrey L. Klein

    IPC分类号： H01L21/304 ,  B24B37/00 ,  C09K13/04 ,  C23F1/00 ,  H01L21/321 ,  H01L21/768 ,  B44C1/22 ,  H01L21/306

    CPC分类号： H01L21/3212

    摘要： Conductive plugs (28) are formed in a semiconductor device (10) using a chemical mechanical polishing (CMP) process. A blanket conductive layer (26), for example of tungsten, is deposited in a plug opening (24). The conductive layer is polished back by CMP using a slurry comprised of either copper sulfate (CuSO.sub.4) or copper perchlorate [Cu(ClO.sub.4).sub.2 ] and an abrasive, such as alumina or silica, and water. In another embodiment, a CMP process using such slurries may be used to form conductive interconnects (50) in a semiconductor device (40).

    摘要翻译： 使用化学机械抛光（CMP）工艺在半导体器件（10）中形成导电插塞（28）。 诸如钨的覆盖层导电层（26）沉积在插头开口（24）中。 使用由硫酸铜（CuSO 4）或高氯酸铜[Cu（ClO 4）2]和研磨剂如氧化铝或二氧化硅和水组成的浆料，通过CMP对导电层进行抛光。 在另一个实施例中，使用这种浆料的CMP工艺可用于在半导体器件（40）中形成导电互连（50）。

    Method for forming inlaid interconnects in a semiconductor device
    5.
    发明授权
    Method for forming inlaid interconnects in a semiconductor device 失效
    在半导体器件中形成镶嵌互连的方法

    公开(公告)号：US5578523A

    公开(公告)日：1996-11-26

    申请号：US444184

    申请日：1995-05-18

    申请人： Robert W. Fiordalice ,  Papu D. Maniar ,  Jeffrey L. Klein

    发明人： Robert W. Fiordalice ,  Papu D. Maniar ,  Jeffrey L. Klein

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L21/44

    CPC分类号： H01L21/7684 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7685 ,  H01L21/76877 ,  Y10S438/959

    摘要： In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to prevent dishing or cusping of the interconnect upon polishing. By allowing the sacrificial polish assisting layer (31) to be removed at close to the same rate as interconnect metal (42) during the final stages of polishing, dishing is avoided. The aluminum nitride layer also facilitates chemical vapor deposition of aluminum as the interconnect metal by providing a more suitable nucleation site for aluminum than exists with silicon dioxide.

    摘要翻译： 在本发明中，镶嵌互连（44）通过化学机械抛光形成。 在层间电介质（30）和互连金属（42）之间形成呈氮化铝层形式的抛光辅助层（31），以防止在研磨时互连件的凹陷或凹陷。 通过在抛光的最后阶段允许牺牲抛光辅助层（31）以与互连金属（42）相同的速率被去除，因此避免了凹陷。 氮化铝层还通过为存在二氧化硅提供比铝更合适的成核位置，促进铝作为互连金属的化学气相沉积。

    LDD transistor process having doping sensitive endpoint etching
    8.
    发明授权
    LDD transistor process having doping sensitive endpoint etching 失效
    具有掺杂敏感端点蚀刻的LDD晶体管工艺

    公开(公告)号：US4978626A

    公开(公告)日：1990-12-18

    申请号：US240013

    申请日：1988-09-02

    申请人： Stephen S. Poon ,  James R. Pfiester ,  Frank K. Baker ,  Jeffrey L. Klein

    发明人： Stephen S. Poon ,  James R. Pfiester ,  Frank K. Baker ,  Jeffrey L. Klein

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L21/823828 ,  H01L29/78 ,  H01L29/7836 ,  H01L27/0928

    摘要： An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.

    摘要翻译： 通过使用确保栅极氧化物层不会被无意蚀刻而不被静电电荷破裂的工艺形成LDD晶体管。 在半导体衬底之上的栅极氧化物层上形成具有不同掺杂水平的至少两个厚度的栅电极材料。 使用化学蚀刻，其中通过监测化学蚀刻反应的化学产品和化学反应物的比例，可以容易地检测到栅电极材料的蚀刻中的特定端点。 在离子注入期间允许一小层栅电极材料保留在栅极氧化物层上方，并且在制造LDD晶体管时形成和去除栅极侧壁间隔物。 在形成大多数LDD晶体管之后，去除栅电极材料的剩余保护厚度，暴露的栅极氧化层暴露于最后的氧化退火步骤。 在其他形式中，形成逆T栅极结构LDD晶体管，并且通过具有减少数量的离子注入步骤的工艺形成LDD晶体管。

    Method for forming a via in a semiconductor device
    10.
    发明授权
    Method for forming a via in a semiconductor device 失效
    在半导体器件中形成通孔的方法

    公开(公告)号：US5702981A

    公开(公告)日：1997-12-30

    申请号：US536537

    申请日：1995-09-29

    申请人： Papu D. Maniar ,  Roc Blumenthal ,  Jeffrey L. Klein ,  Wei Wu

    发明人： Papu D. Maniar ,  Roc Blumenthal ,  Jeffrey L. Klein ,  Wei Wu

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/76834 ,  Y10S438/97

    摘要： A method for forming vias in a semiconductor device improves the resistance and reliability of contacts formed by use of an etch stop layer during the via formation process. An etch stop layer (40), preferably a silicon nitride or aluminum nitride layer, is deposited over conductive interconnect (34). A via (44) is etched in interlayer dielectric (42), stopping on etch stop layer (40). Etch stop layer (40) is then anisotropicly etched to expose the top of conductive interconnect (34), while maintaining a portion of the etch stop layer along a sidewall of the interconnect, and particularly along those sidewall portions which contain aluminum. A conductive plug (54) is then formed in the via, preferably using one or more barrier or glue layers (50). Formation of a tungsten plug using tungsten hexafluoride can then be performed without unwanted reactions between the tungsten source gas and the aluminum interconnect.

    摘要翻译： 用于在半导体器件中形成通孔的方法通过在通孔形成工艺期间通过使用蚀刻停止层来改善形成的触点的电阻和可靠性。 蚀刻停止层（40），优选氮化硅或氮化铝层，沉积在导电互连（34）上。 在层间电介质（42）中蚀刻通孔（44），停止在蚀刻停止层（40）上。 然后对蚀刻停止层（40）进行各向异性蚀刻以暴露导电互连（34）的顶部，同时沿着互连的侧壁，特别是沿着包含铝的侧壁部分保留蚀刻停止层的一部分。 然后，优选地使用一个或多个阻挡层或胶层（50）在通孔中形成导电插塞（54）。 然后可以进行使用六氟化钨形成钨塞，而不会在钨源气体和铝互连之间产生不必要的反应。