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公开(公告)号：US4978626A
公开(公告)日：1990-12-18
申请号：US240013
申请日：1988-09-02
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/823828 , H01L29/78 , H01L29/7836 , H01L27/0928
摘要： An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.
摘要翻译： 通过使用确保栅极氧化物层不会被无意蚀刻而不被静电电荷破裂的工艺形成LDD晶体管。 在半导体衬底之上的栅极氧化物层上形成具有不同掺杂水平的至少两个厚度的栅电极材料。 使用化学蚀刻，其中通过监测化学蚀刻反应的化学产品和化学反应物的比例，可以容易地检测到栅电极材料的蚀刻中的特定端点。 在离子注入期间允许一小层栅电极材料保留在栅极氧化物层上方，并且在制造LDD晶体管时形成和去除栅极侧壁间隔物。 在形成大多数LDD晶体管之后，去除栅电极材料的剩余保护厚度，暴露的栅极氧化层暴露于最后的氧化退火步骤。 在其他形式中，形成逆T栅极结构LDD晶体管，并且通过具有减少数量的离子注入步骤的工艺形成LDD晶体管。
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2.发明授权Method of fabricating MOS transistors using selective polysilicon deposition 失效使用选择性聚硅氧烷沉积制造MOS晶体管的方法
公开(公告)号：US5082794A
公开(公告)日：1992-01-21
申请号：US569097
申请日：1990-08-17
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66583 , H01L29/1033 , H01L29/1045 , H01L29/66553 , H01L29/7836 , H01L29/66537 , Y10S148/122
摘要： In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.
摘要翻译： 在形成轻掺杂漏极（LDD）晶体管时，首先在有源区上的栅极氧化物上形成薄的多晶硅层。 沉积掩模层并选择性地蚀刻以暴露多晶硅层的中间部分。 该结构可以用作导致形成由一次侧壁间隔物形成的逆T晶体管或常规LDD结构的工艺的一部分。 多晶硅层的暴露的中间部分用于通过选择性多晶硅沉积形成多晶硅栅极。 暴露的中间部分可以被植入用于沟道植入，从而提供对源/漏植入物的自对准。 侧壁间隔件可以形成在暴露部分内部以减小通道长度。 这些侧壁间隔物可以是氮化物以在侧壁间隔物和方便使用的低温氧化物（LTO）掩模之间提供蚀刻选择性。
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公开(公告)号：US4984042A
公开(公告)日：1991-01-08
申请号：US309589
申请日：1989-02-13
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/66553 , H01L29/7836 , H01L29/66537
摘要： In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results in a formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.
摘要翻译： 在形成轻掺杂漏极（LDD）晶体管时，首先在有源区上的栅极氧化物上形成薄的多晶硅层。 沉积掩模层并选择性地蚀刻以暴露多晶硅层的中间部分。 这种结构可以用作导致逆T晶体管或由一次性侧壁间隔物形成的常规LDD结构的过程的一部分。 多晶硅层的暴露的中间部分用于通过选择性多晶硅沉积形成多晶硅栅极。 暴露的中间部分可以被植入用于沟道植入，从而提供对源/漏植入物的自对准。 侧壁间隔件可以形成在暴露部分内部以减小通道长度。 这些侧壁间隔物可以是氮化物以在侧壁间隔物和方便使用的低温氧化物（LTO）掩模之间提供蚀刻选择性。
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公开(公告)号：US4852062A
公开(公告)日：1989-07-25
申请号：US101875
申请日：1987-09-28
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/105 , H01L27/115 , H01L27/11543 , H01L29/7885
摘要： An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.
摘要翻译： 具有浮动栅极和控制栅极的可擦除可编程只读存储器（EPROM）单元，其中浮置栅极和控制栅极与衬底中的源极/漏极/漏极/源极区域有意地偏移或不对称。 在编程期间，源极区域是与栅极间隔开的区域，而漏极区域与栅极对准。 该方向产生高栅极电流以提供更快的编程。 在读取操作期间，对准区域现在变为源极，并且间隔开的区域变为漏极以提供用于快速访问的高漏极电流。 本发明的非对称EPROM单元可以使用传统的间隔技术容易地制成。
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公开(公告)号：US4811066A
公开(公告)日：1989-03-07
申请号：US109658
申请日：1987-10-19
申请人： James R. Pfiester , Frank K. Baker
发明人： James R. Pfiester , Frank K. Baker
CPC分类号： H01L29/4983 , Y10S257/903
摘要： A compact, multi-state field effect transistor (FET) cell having a gate with edge portions of a different conductivity type than a central portion of the gate. Both the edge portions and the central portion extend from the source to the drain of the multi-state FET device. This device would have two different threshold voltages (V.sub.T), one where the central portion would turn on first, followed by the edges for the entire gate width to be active to give a second level of current flow. Such devices would be useful in building very compact or high density multi-state read-only-memories (ROMs).
摘要翻译： 一种紧凑的多态场效应晶体管（FET）单元，其具有栅极，该栅极具有与栅极的中心部分不同的导电类型的边缘部分。 边缘部分和中心部分都从多态FET器件的源极延伸到漏极。 该装置将具有两个不同的阈值电压（VT），其中中心部分首先接通，然后是使整个栅极宽度的边缘有效以产生第二电流。 这样的设备在构建非常紧凑或高密度多状态只读存储器（ROM）中将是有用的。
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公开(公告)号：US5661048A
公开(公告)日：1997-08-26
申请号：US408654
申请日：1995-03-21
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/265
CPC分类号： H01L29/4983 , H01L21/823857 , H01L29/1083 , H01L29/42376 , H01L29/4991 , H01L29/66659 , H01L29/7835
摘要： An insulated gate field effect transistor (10) having a reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11) and a drain extension region (25) is formed in the dopant well (13). An oxide layer (26) is formed on the dopant well (13) wherein the oxide layer (26) has a thickness of at least 400 angstroms. A gate structure (61) having a gate shunt portion (32) over a thinned portion of the oxide (26) and a gate extension portion (58) over an unthinned portion of the oxide (26). The thinned portion of the oxide (26) forms a gate oxide of the field effect transistor (10) and the unthinned portion lowers a capacitance of the gate shunt portion (32) of the field effect transistor (10).
摘要翻译： 具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。 掺杂剂阱（13）形成在半导体衬底（11）中，并且在掺杂剂阱（13）中形成漏极延伸区域（25）。 氧化物层（26）形成在掺杂剂阱（13）上，其中氧化物层（26）具有至少400埃的厚度。 栅极结构（61）具有在氧化物（26）的薄化部分上方的栅极分流部分（32）和位于氧化物（26）的未固化部分上的栅极延伸部分（58）。 氧化物（26）的减薄部分形成场效应晶体管（10）的栅极氧化物，并且未固化部分降低场效应晶体管（10）的栅极分流部分（32）的电容。
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7.发明授权Method for forming a multi-layer semiconductor device using selective planarization 失效使用选择性平坦化形成多层半导体器件的方法
公开(公告)号：US5037777A
公开(公告)日：1991-08-06
申请号：US546801
申请日：1990-07-02
IPC分类号： H01L21/3105 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/3105 , Y10S148/133 , Y10S148/161 , Y10S438/978
摘要： The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer. Since the second insulating material remains in only selective areas, the process is termed selective planarization. The method provides the benefit that areas which are to be etched to form contact hole or vias are not planarized, unlike existing blanket planarization methods, and a self-aligned contact is formed between the conductive members to the substrate.
摘要翻译： 所公开的发明是使用选择性平坦化制造多层半导体器件的方法。 根据本发明的一个实施例，导电构件形成在衬底上，并且第一绝缘层沉积到衬底和导电构件上。 具有比第一层的流动温度低的流动温度的第二绝缘层沉积到第一层上。 对光致抗蚀剂掩模进行图案化和显影以形成露出导电构件之间的区域的窗口。 优先蚀刻器件，使得只有第二绝缘层的暴露区域被去除，留下第一绝缘层完好无损。 使用各向异性蚀刻去除第一绝缘层的部分，沿着导电构件的边缘留下间隔物。 去除光致抗蚀剂掩模，并且执行流过第二绝缘层的剩余部分而不是第一层的加热步骤。 由于第二绝缘材料仅保留在选择性区域中，所以该过程称为选择性平面化。 该方法提供了与现有的覆盖平面化方法不同的是要被蚀刻以形成接触孔或通孔的区域不平坦化的优点，并且在导电构件与基底之间形成自对准接触。
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公开(公告)号：US5536674A
公开(公告)日：1996-07-16
申请号：US345891
申请日：1994-11-28
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11
摘要： A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.
摘要翻译： 公开了一种包括浮动节点电容器的静态随机存取存储器单元。 在一个实施例中，存储节点用作浮动节点电容器的第一板，并且导电构件用作浮动节点电容器的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 在另一个实施例中，导电构件用作多个存储单元的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 还公开了用于形成存储单元的工艺。
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公开(公告)号：US5275964A
公开(公告)日：1994-01-04
申请号：US64994
申请日：1993-05-24
申请人： James D. Hayden , Frank K. Baker
发明人： James D. Hayden , Frank K. Baker
CPC分类号： H01L27/1108 , Y10S257/903
摘要： A pair of first and second thin film transistors (TFTs). The transistors are formed from a first continuous, conductive region (38) and a second continuous, conductive region (39) which underlies the first conductive region (38). The first transistor has a source region (50), a drain region (54), and a channel region (52) created from three distinct and separate regions of conductor region (39). The first transistor has a gate region (53) that overlies the channel region (52). The gate region (53) is formed from a distinct region of conductive region (38). The second transistor has a source region (44), a drain region (48), and a channel region (46) which are created from three distinct and separate regions of conductor region (38). The second transistor has a gate region (47) that underlies the channel region (46). The gate region (47) is formed from a distinct region of conductive region (39).
摘要翻译： 一对第一和第二薄膜晶体管（TFT）。 晶体管由位于第一导电区域（38）下方的第一连续导电区域（38）和第二连续导电区域（39）形成。 第一晶体管具有源极区域（50），漏极区域（54）和由导体区域（39）的三个不同且分离的区域形成的沟道区域（52）。 第一晶体管具有覆盖沟道区（52）的栅极区（53）。 栅极区域（53）由导电区域（38）的不同区域形成。 第二晶体管具有由导体区域（38）的三个不同且分离的区域产生的源极区（44），漏极区（48）和沟道区（46）。 第二晶体管具有在沟道区（46）下面的栅极区（47）。 栅极区域（47）由导电区域（39）的不同区域形成。
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公开(公告)号：US5712501A
公开(公告)日：1998-01-27
申请号：US541536
申请日：1995-10-10
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L29/7838 , H01L29/66537
摘要： A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.
摘要翻译： 分级沟道半导体器件（10）包括具有主表面（12）的衬底区域（11）。 源区域（13）和漏极区域（14）形成在衬底区域（11）中并且间隔开以形成沟道区域（16）。 掺杂区域（18）形成在沟道区域（16）中并且与源极区域（13），漏极区域（14）和主表面（12）间隔开。 掺杂区域（18）具有与沟道区域（16）相同的导电类型，但具有较高的掺杂剂浓度。 与现有技术的短沟道结构相比，器件（10）表现出增强的穿通电阻和改进的性能。
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