公开(公告)号：US06558994B2

公开(公告)日：2003-05-06

申请号：US09841564

申请日：2001-03-01

申请人： Randall Cher Liang Cha ,  Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

发明人： Randall Cher Liang Cha ,  Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

IPC分类号： H01L2100

CPC分类号： H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L21/76283 ,  H01L2924/0002 ,  Y10S438/967 ,  H01L2924/00

摘要： A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

公开(公告)号：US06613652B2

公开(公告)日：2003-09-02

申请号：US09805707

申请日：2001-03-14

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

IPC分类号： H01L2130

CPC分类号： H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/12

摘要： A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

公开(公告)号：US06468880B1

公开(公告)日：2002-10-22

申请号：US09805954

申请日：2001-03-15

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

IPC分类号： H01L2130

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  Y10S438/977

摘要： A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions. Next, the stop layer is removed. Lastly, devices are formed in and on the active regions.

摘要翻译： 一种使用晶片接合形成绝缘体上硅（SOI）器件的方法。 提供第一基板，其在第一侧上具有绝缘层。 提供了第二衬底，其具有填充第二衬底中的第一沟槽的第一隔离区域（例如STI）。 接下来，通过将绝缘层粘合到第一隔离区域和第二基板上，将第一和第二基板结合在一起。 然后，在第二基板的第二侧上形成止挡层。 图案化第二基板的阻挡层和第二侧，以在第二基板中形成第二沟槽。 第二沟槽具有由隔离区域至少部分地限定的侧壁，并且第二沟槽露出第二绝缘层。 第二沟槽限定第一隔离区域（STI）上的第一有源区，并在绝缘层上限定第二有源区。 接下来，第二沟槽用绝缘体材料填充到第二隔离区域。 接下来，停止层被去除。 最后，在活动区域​​中形成器件。

公开(公告)号：US06849928B2

公开(公告)日：2005-02-01

申请号：US10327309

申请日：2002-12-19

申请人： Randall Cher Liang Cha ,  Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

发明人： Randall Cher Liang Cha ,  Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

IPC分类号： H01L21/762 ,  H01L23/28

CPC分类号： H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L21/76283 ,  H01L2924/0002 ,  Y10S438/967 ,  H01L2924/00

摘要： A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

摘要翻译： 提供一种绝缘体上半导体器件，其中单个晶片管芯在绝缘体层上包含晶体管以形成完全耗尽的绝缘体上硅器件，并且在半导体晶片上的绝缘体结构上形成半导体岛中的晶体管 形成部分耗尽的绝缘体上硅器件。

公开(公告)号：US08766454B2

公开(公告)日：2014-07-01

申请号：US11466018

申请日：2006-08-21

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

摘要翻译： 提供一种集成电路，其具有形成在其上的第一电介质层的基极。 在第一电介质层上形成第二电介质层。 第三电介质层形成在第二电介质层上的间隔开的条带中。 第一沟槽开口通过第三和第二电介质层形成在第三介电层间隔开的条之间。 第二沟槽开口与通过第一介电层的第一沟槽开口连续地形成在第三介电层的间隔开的条之间。 沟槽开口中的导体金属形成自对准沟槽互连。

公开(公告)号：US07119010B2

公开(公告)日：2006-10-10

申请号：US10128875

申请日：2002-04-23

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

公开(公告)号：US06472697B2

公开(公告)日：2002-10-29

申请号：US10140574

申请日：2002-05-08

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

IPC分类号： H01L2710

CPC分类号： H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

公开(公告)号：US06399471B1

公开(公告)日：2002-06-04

申请号：US09783379

申请日：2001-02-15

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

IPC分类号： H01L2144

CPC分类号： H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

公开(公告)号：US06319767B1

公开(公告)日：2001-11-20

申请号：US09798639

申请日：2001-03-05

申请人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Yeow Kheng Lim

发明人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Yeow Kheng Lim

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139

摘要： A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask. The second metal layer is patterned using the hard mask layer as an etching mask whereby the second metal layer forms a top electrode of the capacitor to complete fabrication of a metal-insulator-metal capacitor.

摘要翻译： 描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。 绝缘层设置在半导体衬底上。 形成复合金属堆叠，其包括覆盖绝缘层的第一金属层，覆盖第一金属层的电容器电介质层，覆盖电容器电介质层的第二金属层和覆盖第二金属层的硬掩模层。 第一光致抗蚀剂掩模形成在硬掩模层上。 使用第一光致抗蚀剂掩模将复合金属堆叠图案化为蚀刻掩模，由此图案化的第一金属层形成电容器的底部电极。 通过等离子体灰化除去第一光致抗蚀剂掩模的一部分，以形成比第一光致抗蚀剂掩模窄的第二光刻胶掩模。 使用第二光致抗蚀剂掩模将硬掩模层图案化为蚀刻掩模。 使用硬掩模层作为蚀刻掩模对第二金属层进行构图，由此第二金属层形成电容器的顶部电极，以完成金属 - 绝缘体 - 金属电容器的制造。

公开(公告)号：US06355563B1

公开(公告)日：2002-03-12

申请号：US09798652

申请日：2001-03-05

申请人： Randall Cher Liang Cha ,  Alex See ,  Yeow Kheng Lim ,  Tae Jong Lee ,  Lap Chan

发明人： Randall Cher Liang Cha ,  Alex See ,  Yeow Kheng Lim ,  Tae Jong Lee ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/76802 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76832

摘要： A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种将低介电常数电介质材料与铜金属化相结合的方法。 金属线设置在半导体衬底上并且在其上具有氮化物覆盖层。 多晶硅层沉积在氮化物层上并被图案化以形成虚拟通孔。 电介质衬垫层共形沉积在氮化物层和虚拟通孔之上。 将具有低介电常数的介电层旋涂在衬层上并覆盖虚拟通孔。 抛光电介质层，从而暴露虚拟通孔。 此后，电介质层被固化，由此形成交联表面层。 去除虚设通孔，从而将通孔的一部分氮化物层露出。 去除暴露的氮化物层。 通孔开口填充有铜层，该铜层在集成电路器件的制造中被平坦化以完成铜金属化。