公开(公告)号：US20170186765A1

公开(公告)日：2017-06-29

申请号：US14998251

申请日：2015-12-26

申请人： Randy J. Koval ,  Hiroyuki Sanda

发明人： Randy J. Koval ,  Hiroyuki Sanda

IPC分类号： H01L27/115 ,  G11C16/26 ,  H01L21/3213 ,  G11C16/08

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L21/32133 ,  H01L21/32134 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

摘要： An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.

公开(公告)号：US09047187B2

公开(公告)日：2015-06-02

申请号：US13536861

申请日：2012-06-28

申请人： Xin Guo ,  Yogesh B. Wakchaure ,  Kiran Pangal ,  Hiroyuki Sanda

发明人： Xin Guo ,  Yogesh B. Wakchaure ,  Kiran Pangal ,  Hiroyuki Sanda

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/10

CPC分类号： G06F11/073 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/1016 ,  G06F11/1068

摘要： Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.

摘要翻译： 缺陷管理逻辑延长了存储系统的使用寿命。 例如，如本文所讨论的，故障检测逻辑检测存储器系统中的故障的发生。 缺陷管理逻辑确定失败的类型，例如失败是婴儿死亡型失败还是迟发型失败。 根据故障类型，缺陷管理逻辑执行不同的操作以延长存储系统的使用寿命。 例如，对于早期生活故障，缺陷管理逻辑可以将块的一部分包括故障退出。 对于后期生活故障，由于读取/写入过多，故障管理逻辑可以将故障块从第一位单元存储密度模式转换为以每位存储单元存储密度模式运行。

公开(公告)号：US09543024B2

公开(公告)日：2017-01-10

申请号：US13995145

申请日：2012-03-29

申请人： Hiroyuki Sanda ,  Kiran Pangal ,  Xin Guo ,  Kaoru Naganuma

发明人： Hiroyuki Sanda ,  Kiran Pangal ,  Xin Guo ,  Kaoru Naganuma

IPC分类号： G06F12/00 ,  G11C16/16 ,  G11C11/56 ,  G11C16/34 ,  G06F12/02

CPC分类号： G11C16/16 ,  G06F12/0246 ,  G11C11/5635 ,  G11C16/3445

摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了在擦除之前非易失性存储器的条件预编程的方法，装置和系统配置。 在一种情况下，该方法包括接收擦除非易失性存储器件的一部分中的信息的请求，其中该部分包括多个存储单元，确定包括在该部分中的多个存储单元中的一个或多个存储单元 对所述非易失性存储器件进行编程，如果所述一个或多个存储单元被确定为被编程，并且擦除所述非易失性存储器件的预编程部分，则对所述非易失性存储器件的所述部分进行预编程。 多个确定的编程存储单元可能不超过预定值。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140297924A1

公开(公告)日：2014-10-02

申请号：US13995145

申请日：2012-03-29

申请人： Hiroyuki Sanda ,  Kiran Pangal ,  Xin Guo ,  Kaoru Naganuma

发明人： Hiroyuki Sanda ,  Kiran Pangal ,  Xin Guo ,  Kaoru Naganuma

IPC分类号： G11C16/16

CPC分类号： G11C16/16 ,  G06F12/0246 ,  G11C11/5635 ,  G11C16/3445

摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了在擦除之前非易失性存储器的条件预编程的方法，装置和系统配置。 在一种情况下，该方法包括接收擦除非易失性存储器件的一部分中的信息的请求，其中该部分包括多个存储单元，确定包括在该部分中的多个存储单元中的一个或多个存储单元 对所述非易失性存储器件进行编程，如果所述一个或多个存储单元被确定为被编程，并且擦除所述非易失性存储器件的预编程部分，则对所述非易失性存储器件的所述部分进行预编程。 多个确定的编程存储单元可能不超过预定值。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20190043960A1

公开(公告)日：2019-02-07

申请号：US16022540

申请日：2018-06-28

申请人： Randy Koval ,  Srikant Jayanti ,  Hiroyuki Sanda ,  Meng-Wei Kuo ,  Srivardhan Gowda ,  Krishna Parat

发明人： Randy Koval ,  Srikant Jayanti ,  Hiroyuki Sanda ,  Meng-Wei Kuo ,  Srivardhan Gowda ,  Krishna Parat

IPC分类号： H01L29/423 ,  H01L27/11556 ,  H01L27/11521 ,  H01L29/06 ,  H01L29/10 ,  H01L29/04 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

摘要： A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

公开(公告)号：US20140006847A1

公开(公告)日：2014-01-02

申请号：US13536861

申请日：2012-06-28

申请人： Xin Guo ,  Yogesh B. Wakchaure ,  Kiran Pangal ,  Hiroyuki Sanda

发明人： Xin Guo ,  Yogesh B. Wakchaure ,  Kiran Pangal ,  Hiroyuki Sanda

IPC分类号： G06F11/07

CPC分类号： G06F11/073 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/1016 ,  G06F11/1068

摘要： Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.

摘要翻译： 缺陷管理逻辑延长了存储系统的使用寿命。 例如，如本文所讨论的，故障检测逻辑检测存储器系统中的故障的发生。 缺陷管理逻辑确定失败的类型，例如失败是婴儿死亡型失败还是迟发型失败。 根据故障类型，缺陷管理逻辑执行不同的操作以延长存储系统的使用寿命。 例如，对于早期生活故障，缺陷管理逻辑可以将块的一部分包括故障退出。 对于后期生活故障，由于读取/写入过多，故障管理逻辑可以将故障块从第一位单元存储密度模式中转换为以每比特存储密度模式运行。