-
1.发明申请Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells 失效用于多级闪存单元中高可靠性数据存储和检索操作的方法和装置公开(公告)号：US20100042772A1
公开(公告)日：2010-02-18
申请号：US12228795
申请日：2008-08-14
CPC分类号： G11C11/5628 , G11C2211/5641
摘要： One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.
摘要翻译： 操作一个或多个多电平NAND闪存单元以仅存储单级数据，并且这些操作通过要求写入上层和第二级的单级操作来实现单级操作的数据状态之间的电荷分离水平的提高 即使只有一位数据被存储，也是较低的页面。 也就是说，第二写入操作增加擦除状态和第一写操作的编程状态之间的浮栅电荷的差异，而不改变闪存单元中的数据。 在一个实施例中，控制器指示闪速存储器执行用于在MLC闪存单元中存储单个数据位的两个写入操作。 在另一个实施例中，闪速存储器识别出单个写入操作被引导到高可靠性存储区域，并且在内部产生所需的多个编程步骤以将至少预定量的电荷放置在指定的浮动栅极上。
-
2.发明授权Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells 失效用于多级闪存单元中高可靠性数据存储和检索操作的方法和装置公开(公告)号：US07941592B2
公开(公告)日：2011-05-10
申请号：US12228795
申请日：2008-08-14
IPC分类号： G06F12/00
CPC分类号： G11C11/5628 , G11C2211/5641
摘要： One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.
摘要翻译： 操作一个或多个多电平NAND闪存单元以仅存储单级数据，并且这些操作通过要求写入上层和第二级的单级操作来实现单级操作的数据状态之间的电荷分离水平的提高 即使只有一位数据被存储，也是较低的页面。 也就是说，第二写入操作增加擦除状态和第一写操作的编程状态之间的浮栅电荷的差异，而不改变闪存单元中的数据。 在一个实施例中，控制器指示闪速存储器执行用于在MLC闪存单元中存储单个数据位的两个写入操作。 在另一个实施例中，闪速存储器识别出单个写入操作被引导到高可靠性存储区域，并且在内部产生所需的多个编程步骤以将至少预定量的电荷放置在指定的浮动栅极上。
-
公开(公告)号：US07681004B2
公开(公告)日：2010-03-16
申请号：US11453293
申请日：2006-06-13
申请人： Randy M. Bonella , Chung W. Lam
发明人： Randy M. Bonella , Chung W. Lam
CPC分类号： G06F13/405
摘要： Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory.
摘要翻译： 存储器模块解决了诸如个人计算机之类的计算设备中主存储器性能和磁盘驱动器性能之间日益增长的差距。 本文公开的存储器模块填补了在最终用户加载存储器模块中的显着更高的存储容量的需求。 这些内存模块可加速应用程序的可用性以及这些应用程序的数据。 这种存储器模块的示例性应用是可用于高清晰度录像机的高容量消费者存储产品。 在各种实施例中，存储器模块包括易失性存储器，非易失性存储器和包括到存储器和各种总线的接口的命令解释器。 第一存储器用作第二存储器的加速缓冲器，并且第二存储器为第一存储器提供非易失性备份。 在一些实施例中，可以中断从第一存储器到第二存储器的数据传输，以提供对第二存储器的读取访问。
-
公开(公告)号：US20100223422A1
公开(公告)日：2010-09-02
申请号：US12697243
申请日：2010-01-30
申请人： Randy M. Bonella , Chung W. Lam
发明人： Randy M. Bonella , Chung W. Lam
CPC分类号： G06F13/405
摘要： Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory.
摘要翻译： 存储器模块解决了诸如个人计算机之类的计算设备中主存储器性能和磁盘驱动器性能之间日益增长的差距。 本文公开的存储器模块填补了在最终用户加载存储器模块中的显着更高的存储容量的需求。 这些内存模块可加速应用程序的可用性以及这些应用程序的数据。 这种存储器模块的示例性应用是可用于高清晰度录像机的高容量消费者存储产品。 在各种实施例中，存储器模块包括易失性存储器，非易失性存储器和包括到存储器和各种总线的接口的命令解释器。 第一存储器用作第二存储器的加速缓冲器，并且第二存储器为第一存储器提供非易失性备份。 在一些实施例中，可以中断从第一存储器到第二存储器的数据传输，以提供对第二存储器的读取访问。
-
公开(公告)号：US07024518B2
公开(公告)日：2006-04-04
申请号：US10100312
申请日：2002-03-13
IPC分类号： G06F12/00
CPC分类号： G11C7/1051 , G06F13/1689 , G06F13/1694 , G11C5/00 , G11C5/025 , G11C7/1012 , G11C7/1066 , G11C2207/108
摘要： Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 128:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer.In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.
-
6.发明授权Buffering and interleaving data transfer between a chipset and memory modules 有权在芯片组和存储器模块之间缓冲和交织数据传输公开(公告)号：US07249232B2
公开(公告)日：2007-07-24
申请号：US10777921
申请日：2004-02-11
申请人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
CPC分类号： G06F13/4234
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译： 公开了在芯片组和存储器数据之间提供电隔离。 本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。 每个存储器模块包括多个存储器等级。 这些缓冲区允许将存储器接口拆分成第一和第二子接口。 第一个子接口位于芯片组和缓冲区之间。 第二个子接口位于缓冲区和内存模块之间。 该方法还包括交织缓冲器的输出，以及配置缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。 第一子接口和第二子接口彼此独立地操作，但是彼此同步。
-
公开(公告)号：US06928571B1
公开(公告)日：2005-08-09
申请号：US09662054
申请日：2000-09-15
申请人： Randy M. Bonella , John B. Halbert
发明人： Randy M. Bonella , John B. Halbert
CPC分类号： G06F13/4072 , G11C29/023 , G11C29/025 , G11C29/028
摘要： Technique and system for adjusting delays between signals. A number of signals are produced, and delays between the signals are determined. Programmable delay elements are used, each driven by a signal indicative of one of the delays. By delaying each of a number of the signals by different amounts, the signals can be caused to arrive at desired times, e.g., in synchronism with one another.
摘要翻译： 调整信号间延时的技术和系统。 产生多个信号，并确定信号之间的延迟。 使用可编程延迟元件，每个由指示延迟之一的信号驱动。 通过以不同的量延迟多个信号中的每一个，可以使信号在期望的时间到达，例如彼此同步。
-
8.发明授权公开(公告)号：US06625687B1
公开(公告)日：2003-09-23
申请号：US09665238
申请日：2000-09-18
申请人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.
摘要翻译： 多个存储器模块通过菊花链接口，为每个存储器模块提供点对点连接。 菊花链中的第一个和最后一个存储器模块都连接到形成环形电路的单独的存储器控制器端口。 一组独特的信号在每个方向连接存储器模块。 每个存储器模块中的结电路提供线路隔离，耦合到菊花链中的相邻存储器模块，或者在菊花链中的第一和最后存储器模块的情况下，存储器模块和存储器控制器以及数据 同步电路 每个结电路提供以及电压转换，使得存储器模块上的存储器件以与存储器控制器不同的电压工作，以及多路复用/解复用，使得较少数量的线路与每个结电路接口。
-
9.发明授权
公开(公告)号：US5446863A
公开(公告)日：1995-08-29
申请号：US168718
申请日：1993-12-16
CPC分类号： G06F12/0835 , G06F12/0811 , G06F13/161
摘要： A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.
摘要翻译： 一种用于减少缓存系统的窥探需求并减少缓存系统中的延迟问题的方法和装置。 当高速缓存发生窥探访问时，如果侦听控制逻辑确定先前的侦听访问涉及同一内存位置行，则侦听控制逻辑不会引导高速缓存窥探此后续访问。 这缓解了缓存的窥探负担，从而提高了在此期间从高速缓存中工作的处理器的效率。 当实现多级缓存系统时，监听控制逻辑引导高速缓存窥探对先前侦听行的某些后续访问，以防止高速缓存一致性问题出现。 还包括减少高速缓存的窥探操作中的延迟问题的延迟降低逻辑。 在每个超出高速缓存的处理器读取，即高速缓存读取未命中之后，逻辑增益用于高速缓存的地址输入的控制用于窥探目的。 缓存不再需要其地址总线用于读取周期，因此读取操作不受阻碍地继续。 此外，高速缓存准备好即将到来的窥探周期。
-
公开(公告)号：US5333293A
公开(公告)日：1994-07-26
申请号：US757701
申请日：1991-09-11
申请人： Randy M. Bonella
发明人： Randy M. Bonella
CPC分类号： G06F15/16
摘要： A synchronous memory controller capable of operating with three different frequency microprocessors and yet providing similar DRAM timings. Input frequencies of 32, 25 and 33 MHz correspond to 16, 25 and 33 MHz microprocessors. Various states are bypassed at certain frequencies to allow the various memory, latch and buffer control signals to be produced uniformly. The memory controller also handles operations from external buses, such as the EISA and ISA buses at the various input frequencies. These external bus cycles are controlled by separate state machines, which also have states bypassed for certain input frequencies.
摘要翻译： 同步存储器控制器，能够与三个不同的频率微处理器一起工作，并提供类似的DRAM时序。 32,25和33 MHz的输入频率对应于16,25和33 MHz微处理器。 各种状态在某些频率旁路，以允许均匀地产生各种存储器，锁存器和缓冲器控制信号。 存储器控制器还处理来自外部总线的操作，例如在各种输入频率下的EISA和ISA总线。 这些外部总线周期由单独的状态机控制，这些状态机也具有绕过某些输入频率的状态。
-
-
-
-
-
-
-
-
-
搜索结果
33 条记录 (耗时 0.088 秒)