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    Method of forming sidewall spacer using dual-frequency plasma enhanced CVD
    1.
    发明授权
    Method of forming sidewall spacer using dual-frequency plasma enhanced CVD 失效
    使用双频等离子体增强CVD形成侧壁间隔物的方法

    公开(公告)号：US07202187B2

    公开(公告)日：2007-04-10

    申请号：US10710257

    申请日：2004-06-29

    申请人： Ravikumar Ramachandran ,  James T. Kelliher ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Ravikumar Ramachandran ,  James T. Kelliher ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L21/469 ,  H01L21/31

    CPC分类号： H01L21/3185 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/823864

    摘要： A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD process, at a temperature in the range 400° C. to 550° C. The process pressure is in the range 2 Torr to 5 Torr. The low frequency power is in the range 0 W to 50 W, and the high frequency power is in the range 90 W to 110 W. The precursor gases of silane, ammonia and nitrogen flow at flow rates in the ratio 240:3200:4000 sccm. The use of the silicon nitride spacer of the invention to form a PFET device having a dual spacer results in a 10%–15% performance improvement compared to a similar PFET device having a silicon nitride spacer formed by a RTCVD process.

    摘要翻译： 用于形成PFET器件的氮化硅间隔物材料和用于制造间隔物的方法包括使用双频等离子体增强CVD工艺，其中温度在通过低温下沉积氮化硅层的范围 双频等离子体增强CVD工艺，温度范围为400°C至550°C。工艺压力范围为2 Torr至5 Torr。 低频功率在0W至50W的范围内，高频功率在90W至110W的范围内。硅烷，氨和氮气的前体气体以240：3200：4000的比例流动 sccm。 与具有通过RTCVD工艺形成的氮化硅间隔物的类似PFET器件相比，使用本发明的氮化硅间隔物形成具有双间隔物的PFET器件导致10％-15％的性能提高。

    High-performance CMOS SOI devices on hybrid crystal-oriented substrates
    5.
    发明授权
    High-performance CMOS SOI devices on hybrid crystal-oriented substrates 失效
    高性能CMOS SOI器件在混合晶体取向衬底上

    公开(公告)号：US07713807B2

    公开(公告)日：2010-05-11

    申请号：US11958877

    申请日：2007-12-18

    申请人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

    发明人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

    摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

    摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

    Curved FINFETs
    6.
    发明授权
    Curved FINFETs 有权
    弯曲的FINFET

    公开(公告)号：US07538391B2

    公开(公告)日：2009-05-26

    申请号：US11621228

    申请日：2007-01-09

    申请人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

    发明人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7843

    摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.

    摘要翻译： 一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。 然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。 接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。 翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的 移动，中央部分不能自由移动。 在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。 因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

    Nanowire field effect transistors
    7.
    发明授权
    Nanowire field effect transistors 有权
    纳米线场效应晶体管

    公开(公告)号：US08536563B2

    公开(公告)日：2013-09-17

    申请号：US12884707

    申请日：2010-09-17

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L29/06

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/84 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.

    摘要翻译： 一种用于形成纳米线场效应晶体管（FET）器件的方法，包括形成绝缘体上硅（SOI）焊盘区域，第二SOI焊盘区域，第三SOI焊盘区域，将第一SOI焊盘区域连接到第一SOI焊盘区域的第一SOI部分 第二SOI焊盘区域和将第二SOI焊盘区域连接到衬底上的第三SOI焊盘区域的第二SOI部分，在第二SOI部分上形成第一硬掩模层，在半导体衬底上形成第一悬浮的纳米线，形成第一 围绕第一悬浮纳米线的一部分构造栅极结构，在第一栅极结构和第一悬置纳米线上图案化第二硬掩模层，去除第一硬掩模层，在半导体衬底上形成第二悬浮纳米线，在第二栅极结构周围形成第二栅极结构 第二悬浮纳米线的一部分，以及去除第二硬掩模层。

    Contacts for Nanowire Field Effect Transistors
    8.
    发明申请
    Contacts for Nanowire Field Effect Transistors 有权
    纳米线场效应晶体管的接触

    公开(公告)号：US20120037880A1

    公开(公告)日：2012-02-16

    申请号：US12856718

    申请日：2010-08-16

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L29/775 ,  H01L21/336

    CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/938

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact.

    摘要翻译： 一种形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的一部分周围形成栅叠层，在栅叠层上形成覆盖层，形成邻近于 栅极堆叠和从栅极堆叠延伸的纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，在器件的暴露部分上形成金属层，在金属层上沉积导电材料，去除硬掩模 层，并且去除导电材料的部分以限定源极区接触和漏极区接触。

    Self-aligned contacts for nanowire field effect transistors
    9.
    发明授权
    Self-aligned contacts for nanowire field effect transistors 有权
    纳米线场效应晶体管的自对准触点

    公开(公告)号：US08097515B2

    公开(公告)日：2012-01-17

    申请号：US12631213

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.

    摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的一部分周围形成栅极结构，在栅极结构上形成覆盖层; 形成邻近所述栅极的侧壁和从所述栅极延伸的纳米线的周围的第一间隔物，在所述覆盖层和所述第一间隔物上形成硬掩模层，去除所述纳米线的暴露部分，在暴露的横截面上外延生长掺杂半导体材料 以形成源极区和漏极区，在外延生长的掺杂半导体材料中形成硅化物材料，并在源极和漏极区上形成导电材料。

    METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE
    10.
    发明申请
    METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE 有权
    具有降低PARASITIC电容的SOI体接触FET的方法和结构

    公开(公告)号：US20090315138A1

    公开(公告)日：2009-12-24

    申请号：US12141276

    申请日：2008-06-18

    申请人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Leland Chang ,  Anthony I. Chou ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L27/12 ,  H01L21/3205

    CPC分类号： H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.

    摘要翻译： 在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。