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    Refrigerator incorporating french doors with rotating mullion bar
    1.
    发明申请
    Refrigerator incorporating french doors with rotating mullion bar 有权
    冰箱内装有旋转竖框的法式门

    公开(公告)号：US20050046319A1

    公开(公告)日：2005-03-03

    申请号：US10650723

    申请日：2003-08-29

    申请人： Raymond Chekal ,  Richard Kirchner ,  Jeffrey O'Halloran ,  Chad Rotter ,  Greg Scorpil ,  Jack Standefer ,  David Stauffer

    发明人： Raymond Chekal ,  Richard Kirchner ,  Jeffrey O'Halloran ,  Chad Rotter ,  Greg Scorpil ,  Jack Standefer ,  David Stauffer

    IPC分类号： F25D11/02 ,  F25D23/02 ,  F25D23/08 ,  A47B96/04

    CPC分类号： F25D11/02 ,  F25D23/02 ,  F25D23/087 ,  F25D2323/021 ,  F25D2400/04

    摘要： A refrigerator includes French-style doors and a rotating mullion. The rotating mullion is mounted to one of the French-style doors through first and second hinge members. Each of the first and second hinge members include first and second hinge elements having corresponding cam members. The cam members include multiple lobes and extend about hinge pins that define an axis of rotation for the mullion. The multiple lobes actually define first and second detent positions for the rotating mullion. A spring biases the first cam member against the second cam member so that the rotating mullion is positively maintained in either the first or second position. The mullion is formed from mating halves, each including a portion of an integrally formed pin element. The pin element travels within a guide element to automatically rotate the mullion between the first and second positions during use.

    摘要翻译： 冰箱包括法式门和旋转竖框。 旋转竖框通过第一和第二铰链构件安装到法国式门之一。 第一和第二铰链构件中的每一个包括具有对应的凸轮构件的第一和第二铰链元件。 凸轮构件包括多个凸起并围绕限定竖框旋转轴线的铰链销延伸。 多个叶片实际上限定了用于旋转竖框的第一和第二制动位置。 弹簧将第一凸轮构件偏置抵靠第二凸轮构件，使得旋转的竖框牢固地保持在第一或第二位置。 竖框由配合半部形成，每个半部包括整体形成的销元件的一部分。 销元件在引导元件内行进，以在使用期间自动旋转第一和第二位置之间的竖框。

    SYSTEM AND METHOD FOR OPTIMIZING ITERATIVE CIRCUIT FOR CYCLIC REDUNDENCY CHECK (CRC) CALCULATION
    4.
    发明申请
    SYSTEM AND METHOD FOR OPTIMIZING ITERATIVE CIRCUIT FOR CYCLIC REDUNDENCY CHECK (CRC) CALCULATION 失效
    用于优化循环冗余校验（CRC）计算的迭代电路的系统和方法

    公开(公告)号：US20070162823A1

    公开(公告)日：2007-07-12

    申请号：US11676653

    申请日：2007-02-20

    申请人： Ming-I Lin ,  David Stauffer

    发明人： Ming-I Lin ,  David Stauffer

    IPC分类号： H03M13/00

    CPC分类号： H03M13/091 ,  H03M13/6508

    摘要： A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block, respective blocks of the first plurality configured for receiving data inputs having respective byte widths ranging from 2N+M to 2N−L+M, where N is equal to log2(w), and M is an offset value, and L is a whole number based on a maximum propagation delay criteria; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, respective blocks of the second plurality configured for receiving data having respective byte widths ranging from 2N−L−1+M to 20; and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input; wherein any number of data input bytes may be processed.

    摘要翻译： 用于生成与通过通信信道传送的宽度为w字节的数据相关联的CRC码字的系统包括第一多个串行耦合码产生块，每个用于基于输入到每个块的数据产生CRC值， 所述第一多个的各个块被配置为用于接收具有范围从2 N + M到2 NL + M的各自的字节宽度的数据输入，其中N等于log＆lt; 2（W），M是偏移值，L是基于最大传播延迟准则的整数; 每个用于基于数据输入生成CRC值的第二多个并行耦合代码生成模块，所述第二多个并行耦合代码生成块被配置用于接收具有范围从2 NL1 + M的相应字节宽度的数据的第二多个块 至2 <0> 以及用于基于所述数据输入在所述第一和第二多个中选择要包括在CRC计算中的特定CRC码生成块的装置; 其中可以处理任何数量的数据输入字节。

    AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS
    5.
    发明申请
    AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS 有权
    自动化模拟测试系统用于串行/ DESERIALIZER数据系统

    公开(公告)号：US20070129920A1

    公开(公告)日：2007-06-07

    申请号：US11275035

    申请日：2005-12-05

    申请人： Francis Kampf ,  Jeanne Trinko-Mechler ,  David Stauffer

    发明人： Francis Kampf ,  Jeanne Trinko-Mechler ,  David Stauffer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022 ,  G01R31/318314

    摘要： Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

    摘要翻译： 本文的实施例提供了一种用于串行器/解串器数据路径系统的自动化仿真测试台生成的方法。 该方法提供用于生成和检查数据路径系统内的数据的事务处理器的数据库，其中事务处理器适用于数据通路系统的任意配置。 数据库提供了每个核心单个事务处理器集合。 接下来，该方法自动从数据库中选择一组事务处理器，以便包含在仿真测试台中。 接下来，该方法通过将所选择的一组事务处理器与数据路径系统相互连接，通过数据路径系统映射第一个数据路径和第二个数据路径。 该方法还包括设置核上的控制引脚以便于数据通过数据路径系统的核心的传播。 随后，控制引脚被跟踪到输入端口和控制寄存器。

    Detection of Frame Marker Quality
    6.
    发明申请
    Detection of Frame Marker Quality 失效
    检测帧标记质量

    公开(公告)号：US20100226420A1

    公开(公告)日：2010-09-09

    申请号：US12397790

    申请日：2009-03-04

    申请人： Etai Adar ,  Michael Bar-Joshua ,  David Stauffer

    发明人： Etai Adar ,  Michael Bar-Joshua ,  David Stauffer

    IPC分类号： H04L27/01 ,  H04B17/00

    CPC分类号： H04L7/042 ,  H04L1/20 ,  H04L7/046

    摘要： For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.

    摘要翻译： 例如，检测帧标记质量的方法包括：在从第一分量发送到公共硬件单元的第二分量的比特流中检测具有不同于由 通信协议; 以及基于所述位模式和所述未损坏帧标记的位模式之间的差异，将质量水平指示符分配给帧标记。

    METHOD, SYSTEM AND PROGRAM PRODUCT FOR BUILDING AN AUTOMATED DATAPATH SYSTEM GENERATING TOOL
    7.
    发明申请
    METHOD, SYSTEM AND PROGRAM PRODUCT FOR BUILDING AN AUTOMATED DATAPATH SYSTEM GENERATING TOOL 失效
    用于建立自动数据系统生成工具的方法，系统和程序产品

    公开(公告)号：US20050257179A1

    公开(公告)日：2005-11-17

    申请号：US10709528

    申请日：2004-05-12

    申请人： David Stauffer ,  Jeanne Trinko-Mechler

    发明人： David Stauffer ,  Jeanne Trinko-Mechler

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： A method, system and program product for building an automated bit-sliced datapath system generating tool so design can be performed at a higher level, and automated generation of the synthesizable HDL representation can be accomplished are disclosed. A method defines datapath system characteristics, defines core/pin rules, and then constructs class-type inference rules that can be used for automatically generating the datapath system. An “orthogonal bundling” technique is used that groups pin by a class, and also by a channel identifier. The class-type inference rule corresponding to each class uses of the following factors to infer appropriate wiring: 1) number and type of pins in the class created by the instantiation of cores by the user; 2) attribute definitions on pins set by library core/pin rules; 3) user selection of “global attributes”; 4) user definition of channel bit order (“link orders”) to imply the order of connection between stages; and 5) user-defined attributes set on pin classes.

    摘要翻译： 可以在更高层次上执行用于构建自动位片数据路径系统生成工具的设计的方法，系统和程序产品，并且可以实现自动生成可综合的HDL表示。 一种方法定义数据路径系统特性，定义核心/引脚规则，然后构建可用于自动生成数据路径系统的类类型推理规则。 使用“正交捆绑”技术，其通过类分组引脚，并且还使用通道标识符。 对应于每个类的类型推理规则使用以下因素来推断适当的布线：1）由用户实例化核心创建的类中的引脚数量和类型; 2）由库核心/引脚规则设置的引脚上的属性定义; 3）用户选择“全局属性”; 4）用户定义通道位顺序（“链接顺序”）以表示阶段之间的连接顺序; 和5）用户定义的属性设置在引脚类上。

    Detection of frame marker quality
    8.
    发明授权
    Detection of frame marker quality 失效
    检测帧标记质量

    公开(公告)号：US08249177B2

    公开(公告)日：2012-08-21

    申请号：US12397790

    申请日：2009-03-04

    申请人： Etai Adar ,  Michael Bar-Joshua ,  David Stauffer

    发明人： Etai Adar ,  Michael Bar-Joshua ,  David Stauffer

    IPC分类号： H04L27/00

    CPC分类号： H04L7/042 ,  H04L1/20 ,  H04L7/046

    摘要： For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.

    摘要翻译： 例如，检测帧标记质量的方法包括：在从第一分量发送到公共硬件单元的第二分量的比特流中检测具有不同于由 通信协议; 以及基于所述位模式和所述未损坏帧标记的位模式之间的差异，将质量水平指示符分配给帧标记。

    SYSTEM AND METHOD FOR DATA PHASE REALIGNMENT
    9.
    发明申请
    SYSTEM AND METHOD FOR DATA PHASE REALIGNMENT 失效
    用于数据相位实现的系统和方法

    公开(公告)号：US20050008110A1

    公开(公告)日：2005-01-13

    申请号：US10604296

    申请日：2003-07-09

    申请人： Sheehan Lake ,  David Stauffer

    发明人： Sheehan Lake ,  David Stauffer

    IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L7/033

    CPC分类号： H04L7/02 ,  H04L7/0012 ,  H04L7/0045 ,  H04L7/0337 ,  H04L7/0338

    摘要： A system and method for aligning data transferred across circuit boundaries having different clock domains. The system includes a buffer circuit comprising a latch for receiving data clocked in a first clock domain and latching the received data in a second clock domain by one of a first edge of a second clock signal, or a second opposite edge of the second clock signal. The first and second clock signals are of the same frequency but operating out of phase. A control circuit receives the first and second clock signals and determines a phase relationship therebetween. The control circuit generates a control signal based on the determined phase relationship which is implemented for selecting one of a rising edge of the second clock signal, or a falling edge of the second clock signal, for latching action in the second clock domain. Reliable data transfer operation is provided for all possible phase relationships of the first and second clock signals.

    摘要翻译： 用于对准跨越具有不同时钟域的电路边界传输的数据的系统和方法。 该系统包括缓冲电路，该缓冲电路包括用于接收以第一时钟域计时的数据的锁存器，并且通过第二时钟信号的第一边缘或第二时钟信号的第二相对边沿将第二时钟域中的接收数据锁存在第二时钟域中 。 第一和第二时钟信号的频率相同，但是不同相位。 控制电路接收第一和第二时钟信号并确定它们之间的相位关系。 控制电路基于所确定的相位关系产生控制信号，该相位关系用于选择第二时钟信号的上升沿或第二时钟信号的下降沿中的一个，用于在第二时钟域中进行锁存动作。 为第一和第二时钟信号的所有可能的相位关系提供可靠的数据传送操作。