公开(公告)号：US20150115269A1

公开(公告)日：2015-04-30

申请号：US14517646

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Yasushi ISHII ,  Tetsuo Adachi

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L23/3107 ,  H01L23/562 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03831 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/09051 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/49052 ,  H01L2224/49113 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20753

Abstract: This invention provides a semiconductor device with improved reliability. A semiconductor chip (semiconductor device) includes a plurality of electrode pads arranged in a plurality of lines extending along a side (chip side) of a perimeter of the semiconductor chip in plan view. Among the electrode pads, the areas of respective electrode pads arranged in a first line along the chip side are smaller than the areas of respective electrode pads arranged in a line located further than the first line from the chip side.

Abstract translation: 本发明提供一种可靠性提高的半导体器件。 半导体芯片（半导体器件）包括布置在平面图中沿着半导体芯片的周边的一侧（芯片侧）延伸的多条线的多个电极焊盘。 在电极焊盘中，沿着芯片侧布置在第一线中的各个电极焊盘的区域小于布置在比芯片侧的第一线更远的线中的各个电极焊盘的区域。