Semiconductor die array structure
    1.
    发明授权
    Semiconductor die array structure 有权
    半导体晶片阵列结构

    公开(公告)号:US08884403B2

    公开(公告)日:2014-11-11

    申请号:US12982376

    申请日:2010-12-30

    摘要: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

    摘要翻译: 根据本发明,通过两个阶段切割晶片来减小或基本消除晶片位移。 在一些实施例中,在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中,在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。 第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度,并且可选地沿着第二组街道切割至小于模具厚度的深度。 第一切割过程的结果是一组带状或模具块,每个包括多个连接的模具,其比单独的单个模具更少受到偏移。 在第二晶片切割过程中,通过沿着第二组街道切割来切割模具。 在第一切割过程之后,并且在第二切割过程之前,可以进行对模移的敏感的附加的模具制备程序。

    Semiconductor Die Separation Method
    2.
    发明申请
    Semiconductor Die Separation Method 有权
    半导体模具分离方法

    公开(公告)号:US20090315174A1

    公开(公告)日:2009-12-24

    申请号:US12323288

    申请日:2008-11-25

    IPC分类号: H01L23/48 H01L21/00

    摘要: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

    摘要翻译: 根据本发明,通过两个阶段切割晶片来减小或基本消除晶片位移。 在一些实施例中,在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中,在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。 第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度,并且可选地沿着第二组街道切割至小于模具厚度的深度。 第一切割过程的结果是一个或多个模具的阵列,每个芯片或多个模具包括多个连接的模具,其比单独的单个模具更少受到偏移。 在第二晶片切割过程中,通过沿着第二组街道切割来切割模具。 在第一切割过程之后,并且在第二切割过程之前,可以进行对模移的敏感的附加的模具制备程序。

    Semiconductor Die Separation Method
    7.
    发明申请
    Semiconductor Die Separation Method 有权
    半导体模具分离方法

    公开(公告)号:US20110101505A1

    公开(公告)日:2011-05-05

    申请号:US12982376

    申请日:2010-12-30

    IPC分类号: H01L23/544 H01L23/52

    摘要: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

    摘要翻译: 根据本发明,通过两个阶段切割晶片来减小或基本消除晶片位移。 在一些实施例中,在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中,在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。 第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度,并且可选地沿着第二组街道切割至小于模具厚度的深度。 第一切割过程的结果是一个或多个模具的阵列,每个芯片或多个模具包括多个连接的模具,其比单独的单个模具更少受到偏移。 在第二晶片切割过程中,通过沿着第二组街道切割来切割模具。 在第一切割过程之后,并且在第二切割过程之前,可以进行对模移的敏感的附加的模具制备程序。

    Semiconductor die separation method
    8.
    发明授权
    Semiconductor die separation method 有权
    半导体芯片分离方法

    公开(公告)号:US07863159B2

    公开(公告)日:2011-01-04

    申请号:US12323288

    申请日:2008-11-25

    IPC分类号: H01L21/00

    摘要: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

    摘要翻译: 根据本发明,通过两个阶段切割晶片来减小或基本消除晶片位移。 在一些实施例中,在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中,在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。 第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度,并且可选地沿着第二组街道切割至小于模具厚度的深度。 第一切割过程的结果是一组带状或模具块,每个包括多个连接的模具,其比单独的单个模具更少受到偏移。 在第二晶片切割过程中,通过沿着第二组街道切割来切割模具。 在第一切割过程之后,并且在第二切割过程之前,可以进行对模移的敏感的附加的模具制备程序。

    ADAPTIVE RATE CONTROL FOR ENCODING OF VARIABLE FRAME RATE VIDEO SOURCES
    10.
    发明申请
    ADAPTIVE RATE CONTROL FOR ENCODING OF VARIABLE FRAME RATE VIDEO SOURCES 有权
    用于编码可变帧速率视频源的自适应速率控制

    公开(公告)号:US20130058398A1

    公开(公告)日:2013-03-07

    申请号:US13618931

    申请日:2012-09-14

    IPC分类号: H04N7/26

    摘要: Techniques for performing rate control for encoding of video frames are provided. A first timestamp that indicates a prior video frame capture time and a second timestamp that indicates a current video frame capture time are received. A time difference between these timestamps is determined. An average video data bit encoding rate is multiplied by the determined time difference to calculate a bit budget. An indication of a number of encoded video data bits of the prior video frame and of any further video frames encoded subsequent to the prior video frame and prior to the current video frame is received. A virtual buffer fill level is adjusted based on a difference between the indicated number of encoded video bits and the calculated bit budget. A quantizer parameter is adjusted based on the adjusted virtual buffer fill level. The current video frame is encoded according to the adjusted quantizer parameter.

    摘要翻译: 提供了执行视频帧编码速率控制的技术。 接收指示先前的视频帧捕获时间的第一时间戳和指示当前视频帧捕获时间的第二时间戳。 确定这些时间戳之间的时间差。 将平均视频数据比特编码率乘以确定的时间差以计算比特预算。 接收先前视频帧的编码视频数据位数以及在先前视频帧之后和当前视频帧之前编码的任何另外的视频帧的指示。 基于所指示的编码视频位数与计算的位预算之间的差异来调整虚拟缓冲器填充电平。 基于调整后的虚拟缓冲区填充级别调整量化参数。 当前视频帧根据调整后的量化参数进行编码。