公开(公告)号：US06740539B2

公开(公告)日：2004-05-25

申请号：US10366149

申请日：2003-02-13

申请人： Richard A. Conti ,  Prakash Chimanlal Dev ,  David M. Dobuzinsky ,  Daniel C. Edelstein ,  Gill Y. Lee ,  Kia-Seng Low ,  Padraic C. Shafer ,  Alexander Simpson ,  Peter Wrschka

发明人： Richard A. Conti ,  Prakash Chimanlal Dev ,  David M. Dobuzinsky ,  Daniel C. Edelstein ,  Gill Y. Lee ,  Kia-Seng Low ,  Padraic C. Shafer ,  Alexander Simpson ,  Peter Wrschka

IPC分类号： H01L5140

CPC分类号： H01L21/28185 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

摘要翻译： 公开了一种在衬底上方具有碳分级层的绝缘体层的结构和方法，其中在衬底上方的每个连续的碳分级层中碳的浓度增加。 绝缘体包括介电常数小于3.3的低k电介质。 碳分级层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘合性。 该结构还可以包括碳分级层之间的稳定界面。 更具体地，碳分级层包括邻近基底的第一层，其碳含量在约5％至20％之间，第一层上方的碳含量在约10％至30％之间，第三层 在第二层上方具有约20％至40％的碳含量。

公开(公告)号：US06570256B2

公开(公告)日：2003-05-27

申请号：US09910380

申请日：2001-07-20

申请人： Richard A. Conti ,  Prakash Chimanlal Dev ,  David M. Dobuzinsky ,  Daniel C. Edelstein ,  Gill Y. Lee ,  Kia-Seng Low ,  Padraic C. Shafer ,  Alexander Simpson ,  Peter Wrschka

发明人： Richard A. Conti ,  Prakash Chimanlal Dev ,  David M. Dobuzinsky ,  Daniel C. Edelstein ,  Gill Y. Lee ,  Kia-Seng Low ,  Padraic C. Shafer ,  Alexander Simpson ,  Peter Wrschka

IPC分类号： H01L2348

CPC分类号： H01L21/28185 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

摘要翻译： 公开了一种在衬底上方具有碳分级层的绝缘体层的结构和方法，其中在衬底上方的每个连续的碳分级层中碳的浓度增加。 绝缘体包括介电常数小于3.3的低k电介质。 碳分级层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘合性。 该结构还可以包括碳分级层之间的稳定界面。 更具体地，碳分级层包括邻近基底的第一层，其碳含量在约5％至20％之间，第一层上方的碳含量在约10％至30％之间，第三层 在第二层上方具有约20％至40％的碳含量。

公开(公告)号：US06869860B2

公开(公告)日：2005-03-22

申请号：US10250092

申请日：2003-06-03

申请人： Michael P. Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth T. Settlemeyer, Jr. ,  Padraic C. Shafer

发明人： Michael P. Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth T. Settlemeyer, Jr. ,  Padraic C. Shafer

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76229

摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。

公开(公告)号：US20080124880A1

公开(公告)日：2008-05-29

申请号：US11534651

申请日：2006-09-23

申请人： Wenhe Lin ,  Randy William Mann ,  Padraic C. Shafer ,  Christopher Vincent Baiocco ,  Zhijoing Luo ,  Haining S. Yang ,  Xiangdong Chen

发明人： Wenhe Lin ,  Randy William Mann ,  Padraic C. Shafer ,  Christopher Vincent Baiocco ,  Zhijoing Luo ,  Haining S. Yang ,  Xiangdong Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form S/D regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the S/D and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode.

摘要翻译： 一些非限制性示例性实施例包括一次性间隔物形成和移除过程以及应力覆盖层过程。 我们在衬底上提供栅极结构。 我们形成邻接至少一个栅极侧壁的一次性间隔物。 我们在一次性间隔物附近形成S / D区域。 我们取出一次性垫片。 我们可以在S / D和门上形成硅化物区域。 在一方面，我们可以在邻近栅极的基板的栅极和表面部分上沉积应力诱导层，其中应力诱导衬垫向栅电极下方的衬底的一部分提供应力。

公开(公告)号：US06664161B2

公开(公告)日：2003-12-16

申请号：US10137268

申请日：2002-05-01

申请人： Michael Patrick Chudzik ,  Jack Allan Mandelman ,  Carl John Radens ,  Rajarao Jammy ,  Kenneth T. Settlemyer, Jr. ,  Padraic C. Shafer ,  Joseph F. Shepard, Jr.

发明人： Michael Patrick Chudzik ,  Jack Allan Mandelman ,  Carl John Radens ,  Rajarao Jammy ,  Kenneth T. Settlemyer, Jr. ,  Padraic C. Shafer ,  Joseph F. Shepard, Jr.

IPC分类号： H01L218242

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L29/945

摘要： The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.

摘要翻译： 本发明是一种在具有由金属硅化物形成的掩埋板电极的半导体衬底内制造沟槽电容器的方法和结构。 在蚀刻到衬底中的沟槽中形成凸缘; 在其上沉积保形金属膜，并对其进行退火以形成与套环自对准的硅化物。 硅胶不会形成在硅胶不直接暴露的环，垫和其它区域，因此金属层可以通过选择性蚀刻从这些区域中去除。