公开(公告)号：US4970413A

公开(公告)日：1990-11-13

申请号：US113944

申请日：1987-10-28

申请人： Richard C. Eden ,  John E. Clark ,  Alan S. Fiedler ,  Frank S. Lee ,  Robert Miller

发明人： Richard C. Eden ,  John E. Clark ,  Alan S. Fiedler ,  Frank S. Lee ,  Robert Miller

IPC分类号： H03K5/003 ,  G05F3/24 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/0952

CPC分类号： H03K19/00384 ,  G05F3/245 ,  G05F3/247 ,  H03K19/018535

摘要： A V.sub.BB input threshold potential with feedback circuitry is used to stabilize all of the logic inputs on an GaAs IC to ECL compatible levels over a normal temperature range and normal power supply variations. The system called "V.sub.BB -Feedback" uses "zero translation delay" direct Capacitor Diode Fet Logic (CDFL) inputs. This is an extension of the CDFL circuit approach in which the voltage across the input level shift circuitry on all inputs is adjusted to maintain a threshold voltage equal to the dc potential on an "extra" V.sub.BB input in spite of variations of temperature, power supply voltages or processing parameters such as MESFET pinchoff voltage. A dc potential (V.sub.BB) is applied to the "extra" V.sub.BB input, which is an additional input that is essentially identical to the actual logic inputs. All of the logic input threshold voltages are then slaved to the V.sub.BB dc potential applied to the "extra" V.sub.BB input. ECL compatability is accomplished by combining a reasonably compliant, but uniform, CDFL voltage shifter with feedback circuitry to maintain the shift voltages at proper levels thereby achieving the desired input logic threshold.

公开(公告)号：US06181157B2

公开(公告)日：2001-01-30

申请号：US08967150

申请日：1997-11-10

申请人： Alan S. Fiedler

发明人： Alan S. Fiedler

IPC分类号： H03K1716

CPC分类号： H04L25/0278 ,  H04L25/0272

摘要： A circuit that provides a termination resistance to a transmission line includes a controllable termination resistor coupled between the transmission line and a termination voltage node. The circuit also includes a control circuit coupled to the controllable termination resistor and to a reference resistor. The control circuit matches the resistance of the controllable termination resistor to the resistance of the reference resistor.

摘要翻译： 提供对传输线路的终端电阻的电路包括耦合在传输线路和终端电压节点之间的可控终端电阻器。 电路还包括耦合到可控终端电阻器和参考电阻器的控制电路。 控制电路将可控终端电阻的电阻与参考电阻的电阻相匹配。

公开(公告)号：US20130007500A1

公开(公告)日：2013-01-03

申请号：US13170444

申请日：2011-06-28

申请人： Alan S. Fiedler

发明人： Alan S. Fiedler

IPC分类号： G06F1/06

CPC分类号： G06F1/08 ,  G06F1/10 ,  H03K19/018521

摘要： In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.

摘要翻译： 在高速I / O数据系统的实施例中，第一计算机芯片包括数据传输系统，第二计算机芯片包括数据接收系统。 数据信道传送NRZ数据信号，并且时钟信道将来自数据传输系统的转发时钟信号传送到数据接收系统。 数据传输系统包括：第一差分串行发射器，用于从脉冲数据产生NRZ数据信号;还包括第二差分串行发射器，用于产生转发的时钟信号。 第一多相传输时钟发生器产生用于第一和第二差分串行发射机的发射时钟信号。 数据接收系统包括数据接收机和解串行器，用于接收和解串行化NRZ数据信号，并且包括多相接收时钟发生器，用于从转发的时钟信号产生用于解串行数据接收器的接收时钟信号 。

公开(公告)号：US06731683B1

公开(公告)日：2004-05-04

申请号：US09677269

申请日：2000-10-02

申请人： Alan S. Fiedler ,  Brett D. Hardy

发明人： Alan S. Fiedler ,  Brett D. Hardy

IPC分类号： H03H730

CPC分类号： H04L25/03159 ,  H04L1/203 ,  H04L7/0058 ,  H04L7/0331 ,  H04L2025/03738

摘要： A serial data communication receiver includes a serial data input, first and second equalizers, first and second capture latch circuits, and an equalization control circuit. The first and second equalizers are coupled to the serial data input and have first and second equalized serial data outputs, respectively. Each equalizer has a frequency response that is variable over a range of frequency response settings. The first and second capture latch circuits are coupled to the first and second equalized serial data outputs, respectively, in a phase-locked loop and have first and second recovered data outputs, respectively. The equalization control circuit measures a data eye size of the second equalized serial data output over the range of frequency response settings of the second equalizer and sets the frequency response of the first equalizer to one of the frequency response settings based on the measured data eye sizes.

摘要翻译： 串行数据通信接收机包括串行数据输入，第一和第二均衡器，第一和第二捕捉锁存电路以及均衡控制电路。 第一和第二均衡器耦合到串行数据输入端，分别具有第一和第二均衡串行数据输出。 每个均衡器具有频率响应，频率响应在频率响应设置的范围内是可变的。 第一和第二捕捉锁存电路分别在锁相环中耦合到第一和第二均衡的串行数据输出，并且分别具有第一和第二恢复的数据输出。 均衡控制电路测量第二均衡器的频率响应设置范围上的第二均衡串行数据输出的数据眼尺寸，并且基于所测量的数据眼尺寸将第一均衡器的频率响应设置为频率响应设置之一 。

公开(公告)号：US06417790B1

公开(公告)日：2002-07-09

申请号：US09782806

申请日：2001-02-14

申请人： Alan S. Fiedler ,  Brett D. Hardy

发明人： Alan S. Fiedler ,  Brett D. Hardy

IPC分类号： H03M900

CPC分类号： H03M9/00 ,  H03K17/04106 ,  H03K17/693

摘要： A data serializer includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs. Each pair of first and second control inputs is driven by first and second logic AND circuits having p-channel output drive transistors.

摘要翻译： 数据串行器包括差分输出级。 差分输出级具有n对第一和第二控制输入，其中每对控制输入对应于n个数据输入之一。 每对第一和第二控制输入由具有p沟道输出驱动晶体管的第一和第二逻辑与电路驱动。

公开(公告)号：US06377079B1

公开(公告)日：2002-04-23

申请号：US09783231

申请日：2001-02-14

申请人： Alan S. Fiedler

发明人： Alan S. Fiedler

IPC分类号： H03K19096

CPC分类号： H03K19/018585

摘要： A data serializer includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs and n is an integer greater than one. Each pair of first and second control inputs is driven by a respective logic AND circuits having a rise time controlled by a first adjustable controlled current source and a fall time controlled by a second adjustable controlled current source.

摘要翻译： 数据串行器包括差分输出级。 差分输出级具有n对第一和第二控制输入，其中每对控制输入对应于n个数据输入中的一个，n是大于1的整数。 每对第一和第二控制输入由具有由第一可调控制电流源控制的上升时间和由第二可调控制电流源控制的下降时间的相应逻辑与电路驱动。

公开(公告)号：US06353338B1

公开(公告)日：2002-03-05

申请号：US09783690

申请日：2001-02-14

申请人： Alan S. Fiedler ,  Brett D. Hardy

发明人： Alan S. Fiedler ,  Brett D. Hardy

IPC分类号： H03K190175

CPC分类号： H03K19/018528 ,  H03K19/0016

摘要： A differential output buffer includes first and second complementary data inputs, an idle input, and a differential output stage having first and second output stage control inputs and first and second differential data outputs. First and second push-pull circuits charge one of the first and second output stage control inputs toward a logic high voltage and discharge the other of the first and second output stage control inputs toward a logic low voltage based on relative logic states of the first and second data inputs. A logic low voltage supply generator is coupled to the idle input and the logic low voltage supply terminal for setting the logic low voltage as a function of the idle input.

摘要翻译： 差分输出缓冲器包括第一和第二互补数据输入，空闲输入和具有第一和第二输出级控制输入和第一和第二差分数据输出的差分输出级。 第一和第二推挽电路将第一和第二输出级控制输入中的一个朝向逻辑高电压充电，并且基于第一和第二输出级控制输入的相对逻辑状态将第一和第二输出级控制输入中的另一个向逻辑低电压放电 第二个数据输入。 逻辑低电压电源发生器耦合到空闲输入和逻辑低电压电源端，用于将逻辑低电压设置为空闲输入的函数。

公开(公告)号：US06490325B1

公开(公告)日：2002-12-03

申请号：US09164245

申请日：1998-09-30

申请人： Alan S. Fiedler ,  Michael O. Jenkins

发明人： Alan S. Fiedler ,  Michael O. Jenkins

IPC分类号： H04B300

CPC分类号： H03H7/38

摘要： A data transmission circuit for transmitting a data stream includes a voltage supply terminal, a resistively terminated, controlled-impedance transmission line and an inductor coupled between the voltage supply terminal and the controlled-impedance transmission line.

摘要翻译： 用于发送数据流的数据传输电路包括电压供给端子，电阻端接的受控阻抗传输线和耦合在电压提供端子和受控阻抗传输线之间的电感器。

公开(公告)号：US5854575A

公开(公告)日：1998-12-29

申请号：US969100

申请日：1997-11-13

申请人： Alan S. Fiedler ,  Daniel J. Baxter

发明人： Alan S. Fiedler ,  Daniel J. Baxter

IPC分类号： H03L7/093 ,  H03L7/107 ,  H03L7/08

CPC分类号： H03L7/093 ,  H03L7/107

摘要： An integrated circuit phase-locked loop includes a phase/frequency detector, a charge pump, and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second VCO control inputs, and has a VCO output which is coupled to the phase/frequency detector. An off-chip loop filter input is coupled between the charge pump and the first VCO control input for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first VCO control input and the second VCO control input. The VCO has a lower voltage-to-frequency gain from the first VCO control input to the VCO output than from the second VCO control input to the VCO output.

摘要翻译： 集成电路锁相环包括串联耦合在一起的相/频检波器，电荷泵和压控振荡器（VCO）。 VCO具有第一和第二VCO控制输入，并且具有耦合到相位/频率检测器的VCO输出。 片外环路滤波器输入耦合在电荷泵和第一VCO控制输入端之间，用于耦合到片外环路滤波器。 片上环路滤波器耦合在第一VCO控制输入端和第二VCO控制输入端之间。 VCO从第一个VCO控制输入到VCO输出的电压 - 频率增益较低，而不是从VCO输出的第二个VCO控制输入。

公开(公告)号：US5805089A

公开(公告)日：1998-09-08

申请号：US734691

申请日：1996-10-21

申请人： Alan S. Fiedler ,  Shoba Krishnan

发明人： Alan S. Fiedler ,  Shoba Krishnan

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A time-division data multiplexer has feedback for adjusting the select clock cross-over voltage. The multiplexer includes a multi-phase clock generator having a plurality of select clock outputs with different phases, a plurality of parallel data inputs and first and second serial data outputs. A first set of gating transistors is coupled between the first data output and a common node. Each transistor in the first set is gated by a corresponding data input and at least one corresponding select clock output. A second set of gating transistors is coupled between the second data output and the common node. Each transistor in the second set is gated by a corresponding data input and at least one corresponding select clock output. A first current source is coupled to the common node. An amplifier has a first input which is coupled to the common node, a second input which is coupled to a reference voltage generator and a cross-over control output which is coupled to the plurality of select clock outputs for adjusting the cross-over voltage of the select clock outputs in response to a comparison of the voltages on the first and second amplifier inputs. A loop filter is coupled to the cross-over control output.

摘要翻译： 时分数据多路复用器具有用于调整选择时钟交叉电压的反馈。 多路复用器包括具有多个具有不同相位的选择时钟输出的多相时钟发生器，多个并行数据输入和第一和第二串行数据输出。 第一组选通晶体管耦合在第一数据输出和公共节点之间。 第一组中的每个晶体管由对应的数据输入和至少一个对应的选择时钟输出选通。 第二组选通晶体管耦合在第二数据输出和公共节点之间。 第二组中的每个晶体管由对应的数据输入和至少一个对应的选择时钟输出选通。 第一电流源耦合到公共节点。 放大器具有耦合到公共节点的第一输入端，耦合到参考电压发生器的第二输入端和耦合到多个选择时钟输出的交叉控制输出端，用于调整交叉电压 所述选择时钟输出响应于所述第一和第二放大器输入端的电压的比较。 环路滤波器耦合到交叉控制输出。